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Phase-margin enhancement technique for recycling folded cascode amplifier

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Abstract

A novel circuit technique for enhancing the phase-margin of the recycling folded cascode amplifier is presented. Compared to the conventional recycling folded cascade, using a high-speed current mirror, the proposed amplifier offers the advantage of cancellation of the first non-dominant pole, allowing the phase-margin to be enhanced without affecting the bandwidth. The proposed amplifier was implemented in CSMC standard 0.18 μm CMOS process. Simulation results show that the phase-margin enhancement of 20° is achieved without limiting the bandwidth.

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Acknowledgment

This work is supported by the NSFC (Grant No. 11227202).

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, People’s Republic of China

    Xiao Zhao, Huajun Fang & Jun Xu

Authors
  1. Xiao Zhao
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  2. Huajun Fang
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  3. Jun Xu
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Correspondence to Xiao Zhao.

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Zhao, X., Fang, H. & Xu, J. Phase-margin enhancement technique for recycling folded cascode amplifier. Analog Integr Circ Sig Process 74, 479–483 (2013). https://doi.org/10.1007/s10470-012-0011-9

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  • DOI: https://doi.org/10.1007/s10470-012-0011-9

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