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Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

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Abstract

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point \((P_{{-1}\,{\rm dB}})\) of −13.5 dBm and the input-referred third-order intercept point (P IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of \(1.45 \times 0.72\) mm2 including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.

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Acknowledgements

This work was supported by the National Science Council (NSC), Taiwan, under the Grant NSC-95-2221-E-009-292. The authors would like to thank the National Chip Implementation Center (CIC), National Applied Research Laboratories, Taiwan, for the fabrication of testing chip. The authors would also like to thank the support of CAD tools HFSS from Ansoft Taiwan.

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Correspondence to Chung-Yu Wu.

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Wu, CY., Wang, WC., Shahroury, F.R. et al. Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end. Analog Integr Circ Sig Process 58, 183–195 (2009). https://doi.org/10.1007/s10470-007-9130-0

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  • DOI: https://doi.org/10.1007/s10470-007-9130-0

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