Abstract
Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.
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Lorenzo, R., Chaudhury, S. LCNT-an approach to minimize leakage power in CMOS integrated circuits. Microsyst Technol 23, 4245–4253 (2017). https://doi.org/10.1007/s00542-016-2996-y
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DOI: https://doi.org/10.1007/s00542-016-2996-y