Skip to main content
Log in

A netlist-level fault-injection tool for FPGAs

Ein Tool zur Injektion von Fehlern in FPGA-Designs auf Netzlisten-Ebene

  • Originalarbeiten
  • Published:
e & i Elektrotechnik und Informationstechnik Aims and scope Submit manuscript

Abstract

A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution.

Zusammenfassung

Tools zur Fehlerinjektion können speziell im Kontext von sicherheitskritischen Applikationen hilfreich sein, um etwa Mechanismen zur Fehlererkennung und -vermeidung zu testen oder das Verhalten einer Applikation im Fehlerfall zu überprüfen. Diese Arbeit beschreibt ein derartiges Werkzeug, das es erlaubt, ein FPGA-Design mit Zusatzlogik zur Fehlerinjektion im Zuge der Implementierungsphase auf Netzlisten-Ebene zu instrumentieren und danach zur Laufzeit Fehler am FPGA einzustreuen. Das vorgestellte Tool fügt sich in einen industriellen FPGA Tool Flow ein, unterstützt Devices verschiedener FPGA-Hersteller und kann durch entsprechende Konfiguration an die verfügbaren FPGA-Ressourcen angepasst werden. Die Arbeit geht auf Unterschiede zu existierenden Lösungen ein, die auf HDL- oder Netzlisten-Ebene, aber auch direkt im FPGA-Konfigurations-Bitstream Fehler injizieren. Schlussendlich werden einige Implementierungsergebnisse präsentiert, welche die Sinnhaftigkeit des vorgestellten Ansatzes belegen.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.
Fig. 3.

Similar content being viewed by others

Notes

  1. This feature has, however, not yet been implemented in the current version of our tool.

References

  1. Altera Corporation (2014): Debugging single event upsets using the fault injection debugger. Application note, document No. QII53026, 2014-06-30.

  2. Baraza, J. C., et al. (2008): Enhancement of fault injection techniques based on the modification of VHDL code. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 16(6), 693–706.

    Article  Google Scholar 

  3. Fibich, C., Wenzl, M., Rössler, P., Taucher, H., Matschnig, M. (2014): On automated generation of checker units from hardware assertion languages. In Proceedings of the microelectronic systems symposium 2014. MESS14, Vienna, 8–9 May 2014, 6 pp.

    Google Scholar 

  4. Grand View Research, Inc. (2014): FPGA (Field-Programmable Gate Array) market analysis by application (automotive, consumer electronics, data processing, industrial, military and aerospace, Telecom) and segment forecasts to 2020. May 2014. San Francisco: Grand View Research Inc. ISBN 978-1-68038-133-7.

    Google Scholar 

  5. Grinschgl, J., et al. (2011): Automatic saboteur placement for emulation-based multi-bit fault injection. In Proceedings of the 6th international workshop on reconfigurable communication-centric systems-on-chip. ReCoSoC, Montpellier, France, 2011, 8 pp.

    Google Scholar 

  6. Hongchao, Z., Long, F., Yue, S. (2008): FITVS—A FPGA-based emulation tool for high-efficiency hardness evaluation. In Proceedings of the 2008 international symposium on parallel and distributed processing with applications. ISPA08, Sydney, Australia, 10–12 Dec. 2008 (pp. 525–531).

    Google Scholar 

  7. Jeitler, M., Delvai, M., Reichör, S. (2009): FuSE—a hardware accelerated HDL fault injection tool. In Proceedings of the 5th southern conference on programmable logic. SPL, Sao Carlos, Brasilia, 1–3 April 2009 (pp. 89–94).

    Google Scholar 

  8. Jha, N. K., Gupta, S. (2003): Testing of digital systems (8th ed.). Cambridge: Cambridge University Press.

    Book  Google Scholar 

  9. Karlsson, J., Arlat, J., Leber, G. (1995): Application of three physical fault injection techniques to the experimental assessment of the MARS architecture. In Proceedings of the 5th IFIP working conference on dependable computing for critical applications. DCCA, Urbana-Champaign, USA, Sept. 1995 (pp. 267–287). Los Alamitos: IEEE Computer Society Press.

    Google Scholar 

  10. Kastensmidt, F. L., Carro, L., Reis, R. (2006): Fault-tolerance techniques for SRAM-based FPGAs. Berlin: Springer. 2006.

    Google Scholar 

  11. Legat, U., Biasizzo, A., Novak, F. (2010): Automated SEU fault emulation using partial FPGA reconfiguration. In Proceedings of the 13th international symposium on design and diagnostics of electronic circuits and systems. DDECS, Vienna, Austria, 14–16 April 2010 (pp. 24–27).

    Chapter  Google Scholar 

  12. Mansour, W., Velazco, R. (2013): An automated SEU fault-injection method and tool for HDL-based designs. IEEE Trans. Nucl. Sci., 60(4), 2728–2733.

    Article  Google Scholar 

  13. Mogollon, J. M., et al. (2011): FTUNSHADES2: a novel platform for early evaluation of robustness against SEE. In 12th European conference on radiation and its effects on components and systems. RADECS, Sevilla, Spain, 19–23 Sept. 2011 (pp. 169–174).

    Chapter  Google Scholar 

  14. Nazar, G. L., Carro, L. (2012): Fast single-FPGA fault injection platform. In Proceedings of the 2012 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems. DFT, Austin, USA, 3–5 Oct. 2012 (pp. 152–157).

    Chapter  Google Scholar 

  15. Nicolaidis, M. (2011): Soft errors in modern electronic systems. Berlin: Springer. 2011.

    Book  Google Scholar 

  16. Pellegrini, A., et al. (2008): CrashTest—a fast high-fidelity FPGA-based resiliency analysis framework. In Proceedings of the IEEE international conference on computer design. ICCD 2008, Lake Tahoe, USA, 12–15 Oct. 2008 (pp. 363–370).

    Google Scholar 

  17. Pomarlan, M. (2007): Evaluating the usefulness of USB for real-time robotics applications. Diploma thesis, Politehnica University Timisoara, Romania, 2007.

  18. Saranli, U., Avci, A., Öztürk, M. C. (2011): A modular real-time fieldbus architecture for mobile robotic platforms. IEEE Trans. Instrum. Meas., 60(3), 916–927. 2011.

    Article  Google Scholar 

  19. Snyder, W. (2015): Veripool: website with open-source Verilog and SystemC tools. Last visited 5/2015. See http://www.veripool.org/.

  20. Xilinx, Inc. (2014): Soft error mitigation controller v4.1. Application note, Document No. PG036, Nov. 19, 2014.

Download references

Acknowledgements

The work described herein was done within the “Josef Ressel Center for Verification of Embedded Computing Systems” (VECS) which is funded by the Austrian Federal Ministry for Science and Research (BM:WFJ), managed by the Christian Doppler Research Association.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Peter Rössler.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Fibich, C., Rössler, P., Tauner, S. et al. A netlist-level fault-injection tool for FPGAs. Elektrotech. Inftech. 132, 274–281 (2015). https://doi.org/10.1007/s00502-015-0315-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00502-015-0315-4

Keywords

Schlüsselwörter

Navigation