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Wake-up latencies for processor idle states on current x86 processors

  • Special Issue Paper
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Computer Science - Research and Development

Abstract

During the last decades various low-power states have been implemented in processors. They can be used by the operating system to reduce the power consumption. The applied power saving mechanisms include load-dependent frequency and voltage scaling as well as the temporary deactivation of unused components. These techniques reduce the power consumption and thereby enable energy efficiency improvements if the system is not used to full capacity. However, an inappropriate usage of low-power states can significantly degrade the performance. The time required to re-establish full performance can be significant. Therefore, deep idle states are occasionally disabled, especially if applications have real-time requirements. In this paper, we describe how low-power states are implemented in current x86 processors. We then measure the wake-up latencies of various low-power states that occur when a processor core is reactivated. Finally, we compare our results to the vendor’s specifications that are exposed to the operating system.

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Notes

  1. The variable core clock is typically derived from a constant reference clock via frequency multiplying circuits, e.g., phase-locked loops (PLL).

  2. The PCI register readings are:

    D18F4 0x118: 0x0107000Bh - settings for C1 (15:0) and C2 (31:16)

    D18F4 0x11C: 0x00000000h - C3 (15:0) not configured

    D18F4 0x128: 0x00005500h - C1 cache flush timer \(=\) 28h (11:5)

    D18F3 0x0DC: 0x05475632h - C2 cache flush timer \(=\) 28h (25:19).

  3. /sys/devices/system/cpu/cpu*/cpuidle/state*/disable.

  4. D18F3 xA8[31:29] PopDownPstate = D18F3 xDC[10:8] HwPstateMaxVal.

    Fig. 6
    figure 6

    C6 states for Bulldozer processor

    Full size image

  5. Each compute unit has its own frequency domain while all CUs share one voltage domain.

  6. The processing of instructions is stopped during the frequency transition as there is no stable clock signal.

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Acknowledgments

This work has been funded by the Bundesministerium für Bildung und Forschung via the research projects CoolSilicon (BMBF 16N10186) and Score-E (BMBF 01IH13001).

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Authors and Affiliations

  1. Center for Information Services and High Performance Computing (ZIH), Technische Universität Dresden, 01062 , Dresden, Germany

    Robert Schöne, Daniel Molka & Michael Werner

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  1. Robert Schöne
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  2. Daniel Molka
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  3. Michael Werner
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Correspondence to Robert Schöne.

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Schöne, R., Molka, D. & Werner, M. Wake-up latencies for processor idle states on current x86 processors. Comput Sci Res Dev 30, 219–227 (2015). https://doi.org/10.1007/s00450-014-0270-z

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