Computer Science - Research and Development

, Volume 29, Issue 3, pp 187–195

Evaluation of CPU frequency transition latency


    • Univ. Versailles St-Quentin en Yvelines
  • Alexandre Laurent
    • Univ. Versailles St-Quentin en Yvelines
  • Benoît Pradelle
    • Univ. Versailles St-Quentin en Yvelines
  • William Jalby
    • Univ. Versailles St-Quentin en Yvelines
Special Issue Paper

DOI: 10.1007/s00450-013-0240-x

Cite this article as:
Mazouz, A., Laurent, A., Pradelle, B. et al. Comput Sci Res Dev (2014) 29: 187. doi:10.1007/s00450-013-0240-x


Dynamic Voltage and Frequency Scaling (DVFS) has appeared as one of the most important techniques to reduce energy consumption in computing systems. The main idea exploited by DVFS controllers is to reduce the CPU frequency in memory-bound phases, usually significantly reducing the energy consumption. However, depending on the CPU model, transitions between CPU frequencies may imply varying delays. Such delays are often optimistically ignored in DVFS controllers, whereas their knowledge could enhance the quality of frequency setting decisions.

The current article presents an experimental study on the measurement of frequency transition latencies. The measurement methodology is presented accompanied with evaluations on three Intel machines, reflecting three distinct micro-architectures. In overall, we show for our experimental setup that, while changing CPU frequency upward leads to higher transition delays, changing it downward leads to smaller or similar transition delays across the set of available frequencies.


DVFSStatistical performance evaluationFrequency transition latency

Copyright information

© Springer-Verlag Berlin Heidelberg 2013