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Soft-error mitigation by means of decoupled transactional memory threads

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Abstract

CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead. Several studies have already proposed fault tolerance for parallel codes. However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches. Our attempt to face this multiple challenge is an architectural design called LBRA (Log-Based Redundant Architecture). Based on a Hardware Transactional Memory architecture, LBRA executes redundant threads which communicate through a pair-shared virtual memory log allocated in cache. Our initial version of LBRA executes these redundant threads in SMT cores. To avoid the performance penalty inherent to this architecture, we propose to decouple their execution in different cores, solving the inter-core communication by means of a log buffer empowered by a simple prefetch strategy. Simulation results using a variety of scientific and multimedia applications show that the execution time overhead of our best design is less than 7 % over a base case without fault tolerance. Additionally, we show that LBRA outperforms previous proposals that we have implemented and evaluated in the same framework.

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Notes

  1. We could increase fault detection granularity to memory operations as well, but this requires a bigger log. Refer to Sect. 4.1.1 for more details.

  2. A conflict occurs when an address appears in the write-set of two transactions or the write-set of one and the read-set of another [38].

  3. Provided that the cache coherence protocol is MESI.

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Acknowledgments

Thanks to the anonymous reviewers for their comments and suggestions which definitely improved this work. This work was jointly supported by the Spanish MINECO and Spanish MEC, as well as European Commission FEDER funds under grant numbers TIN2012-38341-C04-03 and TIN2012-31345.

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  1. Computer Engineering Department, Facultad de Informática, University of Murcia, 30100 , Murcia, Spain

    Daniel Sánchez, Juan M. Cebrián, José M. García & Juan L. Aragón

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  1. Daniel Sánchez
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  2. Juan M. Cebrián
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  3. José M. García
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Correspondence to Daniel Sánchez.

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Sánchez, D., Cebrián, J.M., García, J.M. et al. Soft-error mitigation by means of decoupled transactional memory threads. Distrib. Comput. 28, 75–90 (2015). https://doi.org/10.1007/s00446-014-0215-6

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