Article

Applicable Algebra in Engineering, Communication and Computing

, Volume 18, Issue 3, pp 297-311

When cache blocking of sparse matrix vector multiply works and why

  • Rajesh NishtalaAffiliated withComputer Science Division, University of California at Berkeley Email author 
  • , Richard W. VuducAffiliated withComputer Science Division, University of California at Berkeley
  • , James W. DemmelAffiliated withComputer Science Division, University of California at Berkeley
  • , Katherine A. YelickAffiliated withComputer Science Division, University of California at Berkeley

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Abstract

We present new performance models and more compact data structures for cache blocking when applied to sparse matrix-vector multiply (SpM × V). We extend our prior models by relaxing the assumption that the vectors fit in cache and find that the new models are accurate enough to predict optimum block sizes. In addition, we determine criteria that predict when cache blocking improves performance. We conclude with architectural suggestions that would make memory systems execute SpM × V faster.

Keywords

Performance optimization Sparse matrix multiplication Memory hierarchies Performance modeling