Abstract
In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module “inverse Schmitt trigger” to drive the pull-up transistors of conventional HVLS. As a result, the “Miller Plateau” caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5 \(\upmu \)m high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3 ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.
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References
M. Abdelhamid, F. Hussien, M. Aboudina, Charge-compensated correlated level shiftering for single-stage opamps. Electron. Lett. 51(11), 817–818 (2015)
L. Balogh, Design And Application Guide For High Speed MOSFET Gate Drive Circuits
R. Brodersen et al., Design issues for dynamic voltage scaling. in Proceedings of 2000 International Symposium Low Power Electronics and Design (ISLPED00) (2000), pp. 9–14
J. Buyle, V. De Gezelle, B. Bakeroot, J. Doutreloigne, A new type of level-shifter for n-type high-side switches used in high-voltage switching ADSL line drivers. in Proceedings of IEEE International Conference Electronics Circuits and Systems (2008), pp. 954–957
B. Choi, Enhancement of current driving capability in data driver ICs for plasma display panels. IEEE Trans. Consum. Electron. 55, 992–997 (2009)
M.J. Declerq, M. Schubert, F. Clement, 5V-to-75V CMOS output interface circuits. in IEEE International Solid-State Circuits Conference (ISSCC’93) Digest of Technical Papers (1993), pp. 162–163
J. Doutreloigne, A fully integrated ultra-low-power high-voltage driver for bistable LCDs. in Proceedings of IEEE International Symposium VLSI Design Automation and Test (2006), pp. 1–4
I.M. Filanovsky, H. Baltes, CMOS Schmitt trigger design. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 41(1), 46–49 (1994)
B.R. Gregoire, U.K. Moon, An over-60 dB true rail-to-rail performance using correlated level shiftering and an opamp with only 30 dB loop gain. IEEE J. Solid-State Circuits 43(12), 2620–2630 (2008)
Y. Kanno, H. Mizuno, K. Tanaka, T. Watanabe, Level converters with high immunity to power supply bouncing for high-speed sub-1-V LSIs. in Symposium on VLSI Circuits (2000), pp. 202–203
M. Khorasani, L. van den Berg, P. Marshall, M. Zargham, V. Gaudet, D. Elliott, S. Martel, Low-power static and dynamic high-voltage CMOS level-shifter circuits. in ISCAS IEEE International Symposium on Circuits and Systems (2008), pp. 1946–1949
J.P. Kulkarni, K. Kim, K. Roy, A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J. Solid-State Circuits 42(10), 2303–2313 (2007)
J.P. Kulkarni, K. Roy, Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design. IEEE Trans. Very Large Scale Integr. Syst. 20(2), 319–332 (2012)
D.O. Larsen, P. Llimos Muntal, I.H.H. Jorgensen, E. Bruun, High-voltage pulse-triggered SR latch level-shifter design considerations. in NORCHIP (2014), pp. 1–6
Z. Liu, H. Lee, A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shiftering and dynamic timing control for ZVS-based synchronous power converters. in IEEE Custom Integrated Circuits Conference (CICC) (2013), pp. 1–4
Z. Liu, L. Cong, H. Lee, Design of on-chip gate drivers with power-efficient high-speed level shiftering and dynamic timing control for high-voltage synchronous switching power converters. IEEE J. Solid-State Circuits 50(6), 1463–1477 (2015)
Y. Moghe, T. Lehmann, T. Piessens, Nanosecond delay floating high voltage level shifterers in a 0.35 m HV-CMOS technology. IEEE J. Solid-State Circuits 46(2), 485–497 (2011)
D. Pan, H.W. Li, B.M. Wilamowski, A low voltage to high voltage level shifterer circuit for MEMS application. in University/Government/Industry Microelectronics Symposium (2003)
B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill Inc., New York, 2001)
A. Shapiro, E.G. Friedman, Power efficient level shifterer for 16 nm FinFET near threshold circuits. IEEE Trans. Very Large Scale Integr. Syst. 24, 774–778 (2015)
E. Tabasy, M. Kamarei, S. Ashtiani, S. Palermo, Sequential correlated level shiftering: a switched-capacitor approach for high-accuracy systems. IEEE Trans. Circuits Syst. II Express Briefs 60(12), 857–861 (2013)
S.C. Tan, X.W. Sun, Low power CMOS level shifterers by bootstrapping technique. Electron. Lett. 38(16), 876–878 (2002)
Unisonic Technologies Co. Ltd. (UTC) 0.5um 5V/40V/100V BCD process SPICE model
J. Wittmann, T. Rosahl, B. Wicht, A 50V high-speed level shifterer with high dv/dt immunity for multi-MHz DCDC converters. in European Solid State Circuits Conference (ESSCIRC) (ESSCIRC , 2014), pp. 151–154
S.N. Wooters, B.H. Calhoun, T.N. Blalock, An energy-efficient subthreshold level converter in 130-nm CMOS. IEEE Trans. Circuits Syst. II. Express Briefs 57(4), 290–294 (2010)
J. Zhou et al., An ultra-low voltage level shifterer using revised Wilson current mirror for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. IEEE Trans. Circuits Syst. I 62(3), 697–706 (2015)
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This work is supported by the Fundamental Research Funds for the Central Universities of China under the Grant Number JB150222.
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Lai, X., Zhong, L., Xu, D. et al. A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level. Circuits Syst Signal Process 36, 3598–3615 (2017). https://doi.org/10.1007/s00034-016-0488-z
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DOI: https://doi.org/10.1007/s00034-016-0488-z