Abstract
This paper presents a dual-wideband, common-gate, cascode low-noise amplifier (LNA) using gain–bandwidth product optimization technique. This approach shrinks the aspect ratio of the cascode MOS device, thereby reducing the equivalent parasitic capacitance of the resonator load to optimize the gain–bandwidth product of the LNA. The input impedance of the proposed LNA is analyzed, and the noise factor is well predicted through analytical equations. Measurement results that show well agreement with post-simulation results demonstrate the feasibility of this technique. In low-band mode, experimental results presented a maximum \(\left| S_{21} \right| \) of 13.4 dB over a \(-\)3-dB bandwidth of 3.1–4.8 GHz with a minimum noise figure of 4.5 dB. In high-band mode, the proposed LNA achieved a maximum \(\left| S_{21} \right| \) of 13.6 dB with a minimum noise figure of 6.2 dB over a \(-\)3-dB bandwidth of 7.3–9.4 GHz. A test chip with a die area of 0.83 mm\(^{2}\) was fabricated using a 0.18 \(\upmu \)m CMOS process. The proposed dual-wideband LNA consumes 9.1 mW, excluding the buffer, from a supply voltage of 1.8 V.
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The authors would like to thank the Chung Yuan Christian University for financial support, and thank National Chip Implementation Center (CIC), Hsin-Chu, Taiwan, for chip fabrication and measurement support.
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Chen, CC., Wang, YC. A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique. Circuits Syst Signal Process 36, 495–510 (2017). https://doi.org/10.1007/s00034-016-0322-7
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DOI: https://doi.org/10.1007/s00034-016-0322-7