Abstract
Wireless communication standards make use of parallel turbo decoder for higher data rate at the cost of large hardware resources. This paper presents a memory-reduced back-trace technique, which is based on a new method of estimating backward-recursion factors, for the maximum a posteriori probability (MAP) decoding. Mathematical reformulations of branch-metric equations are performed to reduce the memory requirement of branch metrics for each trellis stage. Subsequently, an architecture of MAP decoder and its scheduling based on the proposed back trace as well as branch-metric reformulation are presented in this work. Comparative analysis of bit-error-rate (BER) performances in additive white Gaussian noise channel environment for MAP as well as parallel turbo decoders are carried out. It has shown that a MAP decoder with a code rate of 1/2 and a parallel turbo decoder with a code rate of 1/3 have achieved coding gains of 1.28 dB at a BER of 10\(^{-5}\) and of 0.4 dB at a BER of 10\(^{-4}\), respectively. In order to meet high-data-rate benchmarks of recently deployed wireless communication standards, very large scale integration implementations of parallel turbo decoder with 8–64 MAP decoders have been reported. Thereby, savings of hardware resources by such parallel turbo decoders based on the suggested memory-reduced techniques are accounted in terms of complementary metal oxide semiconductor transistor count. It has shown that the parallel turbo decoder with 32 and 64 MAP decoders has shown hardware savings of 34 and 44 % respectively.
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References
C. Benkeser, Power efficiency and the mapping of communication algorithms into VLSI. Masters thesis, ETH Zurich, Switzerland, (2010)
C. Berrou, A. Glavieux, P. Thitimajshima, Near Shannon limit error-correcting coding and decoding: turbo-codes, in Proceedings of the International Conference Communications, pp. 1064–1070 (1993)
C. Benkeser, A. Burg, T. Cupaiuolo, Q. Huang, Design and optimization of an HSDPA turbo decoder ASIC. IEEE J. Solid State Circuits 44, 98–106 (2009)
L. Bahl, J. Cocke, F. Jelinek, J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate. IEEE Trans. Inf. Theory 20, 284–287 (1974)
S. Benedetto, D. Divsalar, G. Montorsi, F. Pollara, Soft-output decoding algorithms in iterative decoding of turbo codes. in Report JPL TDA Progress, pp. 42–124 (1996)
M. Cheol, I.-C. Park, SIMD processor-based turbo decoder supporting multiple third-generation wireless standards. Journal 15, 801–810 (2007)
R. Dobkin, M. Peleg, R. Ginosar, Parallel VLSI architecture for MAP turbo decoder, in Proceedings of the IEEE International Symposium Personal, Indoor Mobile Radio Communication, pp. 15–18 (2002)
G.D. Forney Jr, The viterbi algorithm. Proc. IEEE 61, 268–278 (2005)
J.F. Hayes, T.M. Cover, J.B. Riera, Optimal sequence detection and optimal symbol-by-symbol detection: similar algorithms. IEEE Trans. Commun. 30, 152–157 (1982)
J. Hagenauer, P. Hoeher, A Viterbi Algorithm with Soft-Decision Outputs and its Applications, Proceedings of the 3rd IEEE Global Telecommunication Conference, Dallas, TX, pp. 1680–1686 (1989)
L. Hanzo, T.H. Liew, B.L. Yeap, Turbo Coding, Turbo Equalisation and Space-Time Coding for Transmission over Fading Channels (Wiley, England, 2003)
S.M. Karim, I. Chakrabarti, High throughput turbo decoder using pipelined parallel architecture and collision free interleaver. IET Commun. 6, 1416–1424 (2012)
S. Kumawat, R. Shrestha, N. Daga, R.P. Paily, High-throughput LDPC-decoder architecture using efficient comparison techniques and dynamic multi-frame processing schedule. IEEE Trans. Circuits Syst. I Regul. Pap. 62, 1421–1430 (2015)
J.P. Kulkarni, K. Kim, K. Roy, A 160 mV robust schmitt trigger based subthreshold SRAM. IEEE J. Solid State Circuits 42, 2303–2313 (2007)
L. Lee, Real-time minimal-bit-error probability decoding of convolutional codes. IEEE Trans. Commun. 22, 146–151 (1974)
C.-C. Lin, Y.-H. Shih, H.-C. Chang, C.-Y. Lee, A low power turbo/viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14, 426–430 (2006)
C.-H. Lin, C.-Y. Chen, T.-H. Tsai, A.-Y. Wu, Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder. IEEE Trans. Circuits Syst. I Reg. Pap. 56, 1005–1016 (2009)
Y. Li, B. Vucetic, Y. Sato, Optimum soft-output detection for channels with intersymbol interference. IEEE Trans. Inf. Theory 41, 704–713 (1995)
LTE: Evolved Universal Terrestrial Radio Access (E-UTRA): Multiplexing and Channel Coding (3GPP TS 36.212 version 10.0.0 Release 10) (2008)
G. Masera, G. Piccinini, M.R. Roch, M. Zamboni, VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 369–379 (1999)
G. Masera, M. Mazza, G. Piccinini, F. Viglione, M. Zamboni, Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10, 279–285 (2002)
H. Michel, A. Worm, N. Wehn, Influence of quantization on the bit-error performance of turbo-decoders. Proc. IEEE Veh. Technol. Conf. 1, 581–585 (2000)
X. Ma, A. Kavcic, Path partitions and forward-only trellis algorithms. IEEE Trans. Inf. Theory 49, 38–52 (2003)
M. Martina, G. Masera, State metric compression techniques for turbo decoder architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 58, 1119–1128 (2011)
J.G. Proakis, Digital Communications, Reading, 2nd edn. (McGraw-Hill, New York, 1989)
C.E. Shannon, A mathematical theory of communication: part-I. Bell Syst. Tech. J. 21, 379–423 (1948)
C.E. Shannon, A mathematical theory of communication: part-II. Bell Syst. Tech. J. 21, 623–656 (1948)
C. Studer, C. Benkeser, S. Belfanti, Q. Huang, Design and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE. IEEE J. Solid State Circuits 46, 8–17 (2011)
Y. Sun, J.R. Cavallaro, efficient hardware implementation of a highly-parallel 3gpp lte/lte-advance turbo decoder. Integr. VLSI J. 44, 305–315 (2011)
Y. Sun, Y. Zhu, M. Goel, J.R. Cavallaro, Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards, in International Conference on Applied-Specific System, Architecture and Processors, pp. 209–214 (2008)
R. Shrestha, R.P. Paily, High-throughput turbo decoder with parallel architecture for LTE wireless communication standards. IEEE Trans. Circuits Syst. I Regul. Pap. 61, 2699–2710 (2014)
S. Talakoub, L. Sabeti, B. Shahrrava, M. Ahmadi, An improved Max-Log-MAP algorithm for turbo decoding and turbo equalization. IEEE Trans. Instrum. Meas. 56, 1058–1063 (2007)
T.-H. Tsai, C.-H. Lin, A new memory-reduced architecture design for Log-MAP algorithm in turbo decoding, in IEEE 6th CAS Symposium on Emerging Technologies: Mobile and Wireless Communications, vol 2, pp. 607–610 (2004)
T-H. Tsai, C-H. Lin, A.-Y. Wu, A memory-reduced Log-MAP kernel for turbo decoder, in IEEE International Symposium on Circuits and Systems (ISCAS), vol 2, pp. 1032–1035 (2005)
F. Vasefi, Z. Abid, Low power n-bit adder and multiplier using lowest-number-or-transistor 1-bit adders, in Canadian Conference on Electrical and Computer Engineering, pp. 1731–1734 (2005)
C.-C. Wong, H.-C. Chang, High-efficiency processing schedule for parallel turbo decoders using QPP interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. 58, 1412–1420 (2011)
C.-C. Wong, H.-C. Chang, Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system. IEEE Trans. Circuits Syst. II Exp. Briefs 57, 566–570 (2010)
C.-C. Wong, M.-W. Lai, C.-C. Lin, H.-C. Chang, C.-Y. Lee, Turbo decoder using contention-free interleaver and parallel architecture. IEEE J. Solid State Circuits 45, 422–432 (2010)
J.P. Woodard, L. Hanzo, Comparative study of turbo decoding techniques: an overview. IEEE Trans. Veh. Technol. 49, 2208–2233 (2000)
N.H.E. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Reading (Pearson-Addison Wesley, MA, 2005)
Y. Wu, B.D. Woerner, T.K. Blankenship, Data width requirements in SISO decoding with modulo normalization. IEEE Trans. Commun. 49, 1861–1868 (2001)
Z. Wang, Z. Chi, K.K. Parhi, Area-efficient high-speed decoding scheme for turbo decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10, 902–912 (2002)
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Shrestha, R., Paily, R. Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. Circuits Syst Signal Process 35, 2832–2854 (2016). https://doi.org/10.1007/s00034-015-0168-4
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DOI: https://doi.org/10.1007/s00034-015-0168-4