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A CMOS Micro-power and Area Efficient Neural Recording and Stimulation Front-End for Biomedical Applications

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Abstract

This paper presents an ultra-low power and small area analog front-end for an implantable multichannel neural signal recording and stimulation interface, to be used in wirelessly powered implantable Brain-Machine Interfaces. For a given functionality and performance, area, power, and noise-response are the three critical parameters that define the suitability of a design for implantation. The three main components of a typical neural implant are the analog front-end, the digital processor, and the wireless data and power transceiver. Among them, neural front-end is the most power and area hungry module. This paper presents an 8-channel analog front-end prototype for simultaneous recording and stimulation, employing a novel architecture which significantly improves power and area consumption of the chip over current state of the art. In contrast to published architectures, the multichannel recording path is centered on a single super-performing tunable gain-bandwidth amplifier instead of employing a separate stand-alone amplifier for each electrode. The resulting circuitry requires smaller area and less power compared to all previously published designs. Designed in 0.5 \(\upmu \)m CMOS with VDD of 1.8 V, the 8-channel recording path consume a total of 77 \(\upmu \)W of power and a net area of 0.24 mm\(^{2}\), allowing scalability to a high channel count. The stimulation path utilizes 8 stimulators, each employing an 8-bit multibias DAC with a current amplifier to drive electrode–electrolyte high impedance load. Each stimulator consumes full scale power of 224 \(\upmu \)W and entire stimulation path occupies an area of 0.32 mm\(^{2}\).

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Acknowledgments

The authors would like to acknowledge technical help by Prof. Andrew Mason and Mr. Yuning Yang from Department of Electrical and Computer Engineering, Michigan State University, East Lansing, USA.

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Authors and Affiliations

  1. Department of Electrical Engineering, School of Electrical Engineering and Computer Sciences, National University of Sciences and Technology, Islamabad, Pakistan

    Sami Ur Rehman & Awais Mehmood Kamboh

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  1. Sami Ur Rehman
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  2. Awais Mehmood Kamboh
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Correspondence to Sami Ur Rehman.

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Rehman, S.U., Kamboh, A.M. A CMOS Micro-power and Area Efficient Neural Recording and Stimulation Front-End for Biomedical Applications. Circuits Syst Signal Process 34, 1725–1746 (2015). https://doi.org/10.1007/s00034-014-9935-x

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  • DOI: https://doi.org/10.1007/s00034-014-9935-x

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