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FPGA Resource Efficient M-PSK Detector for Large MIMO and Multiuser Systems

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Abstract

An M-ary PSK detector, named multiple-phase detector (MPD), is presented that is efficient for both MIMO and multiuser detection, particularly when the number of transmit antennas/users is high. The detector is based on a novel iterative phase descent search (PDS) algorithm. The PDS algorithm arrives at a solution using coordinate descent iterations, where coordinates are the unknown symbol phases, and the solution is constrained to a unit magnitude. In the MPD, the PDS is used multiple times with different initializations; the solution with the minimum cost is then chosen as the final MPD solution. Numerical results show that in a variety of scenarios the MPD performance is close to the optimal performance, whereas its complexity is lower than that of advanced techniques. We present a hardware architecture and FPGA implementation of the MPD. The proposed architecture maximizes the processing speed and minimizes the programmable logic resources. The proposed design requires as few as about \(330\) Xilinx logic slices for \(32\times {32}\) and \(64\times {64}\) MIMO systems and supports a speed of 450 MHz. The fixed-point implementation demonstrates a detection performance which is very close to the performance of the floating point counterpart.

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Acknowledgments

This paper was supported in part by the National Natural Science Foundation of China under the Grant no. 61301149 and the Funds of Henan Provincial Department of Education by Grant no. 13A510627, and the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry.

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Correspondence to Zhi Quan.

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Quan, Z., Liu, J. & Zakharov, Y. FPGA Resource Efficient M-PSK Detector for Large MIMO and Multiuser Systems. Circuits Syst Signal Process 34, 1613–1634 (2015). https://doi.org/10.1007/s00034-014-9920-4

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  • DOI: https://doi.org/10.1007/s00034-014-9920-4

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