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Investigation of Noise-Margin-Enhanced and Low-Power Memory Techniques for SoC Applications

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Abstract

A new memory design with a simple six-transistor memory cell achieves an enhanced read static noise margin. Based on using “pre-equalize” rather than “pre-charge” at the beginning of a read operation, the cross-coupled inverters of the memory cell have a switching threshold close to that of the conventional CMOS inverter circuit, thus achieving both compactness and increased data stability. The proposed can also potentially dramatically decrease power dissipation in conventional memory counterparts. Both simulations and measurements were carried out as proof of concept. The proposed memory hardware techniques are simple to implement and highly practical, making it quite competitive with other currently used methods.

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Acknowledgments

This study was supported in part by the National Science Council (NSC), Taiwan under Grant NSC 102-2218-E-182-003-, and by the Ministry of Science and Technology (MOST), Taiwan, under Grant MOST 103-2221-E-182-070-. Additional support was provided by Chang Gung University (CGU) under contracts UERPD2D0011 and UERPD2D0051.

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Authors and Affiliations

  1. Department of Electrical Engineering, School of Electrical and Computer Engineering, College of Engineering, Chang Gung University, Taoyuan, 333, Taiwan

    Cihun-Siyong Alex Gong

  2. Portable Energy System Group, Green Technology Research Center, College of Engineering, Chang Gung University, Taoyuan, 333, Taiwan

    Cihun-Siyong Alex Gong

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  1. Cihun-Siyong Alex Gong
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Correspondence to Cihun-Siyong Alex Gong.

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Gong, CS.A. Investigation of Noise-Margin-Enhanced and Low-Power Memory Techniques for SoC Applications. Circuits Syst Signal Process 34, 1115–1128 (2015). https://doi.org/10.1007/s00034-014-9898-y

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  • DOI: https://doi.org/10.1007/s00034-014-9898-y

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