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A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \(\mu \)m CMOS

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Abstract

A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed for UWB radar sensing applications. The receiver front-end consists of a full UWB band low-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertion loss and provides a \(-\)30 dB isolation. The diplexer switch was co-designed with the receiver input matching network to optimize the power matching while simultaneously achieving good noise matching performance. The receiver low-noise amplifier provides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. The overall receiver front-end consumes an average power of 13 mW. The core area of the transceiver circuit is 500 \(\mu \)m by 700 \(\mu \)m.

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Acknowledgments

The authors would like to thank CMC Microsystems in Canada for the design tools and fabrication. This project is supported by the Natural Sciences and Engineering Research Council of Canada under Strategic Project Grant number STPGP 350545.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, SK, Canada

    Xubo Wang, Anh Dinh & Daniel Teng

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  1. Xubo Wang
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  2. Anh Dinh
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  3. Daniel Teng
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Correspondence to Xubo Wang.

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Wang, X., Dinh, A. & Teng, D. A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \(\mu \)m CMOS. Circuits Syst Signal Process 33, 1669–1687 (2014). https://doi.org/10.1007/s00034-013-9726-9

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  • DOI: https://doi.org/10.1007/s00034-013-9726-9

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