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Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations

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Abstract

In most real-time DSP applications, high performance is a prime target. Here, performance may be interpreted as a combination of higher speed, lower power consumption, sufficient precision, and VLSI area efficiency. It has been experienced that efficient digital multiplication is a prerequisite for high-speed DSP applications. The MDLNS, which has similar properties to the classical LNS, is an alternative approach to conventional number systems for performing multiplication, through using parallel small adders. In addition, by applying recursive multiplication scheme, larger word length multiplication can be performed by use of several small multipliers. The concept of recursive multiplication can be applied to 2DLNS structures, resulting in more efficient digital multipliers. In this work, the recursive 2DLNS-based multipliers have been applied to FIR filter design. These applications demonstrate the superiority of our architectures in terms of VLSI area and power consumption.

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Acknowledgements

The authors acknowledge financial support from the Natural Sciences and Engineering Council (NSERC-CRD) and the important contribution of CMC Microsystems for their support of design tools.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, N9B 3P4, Canada

    Mahzad Azarmehr & Majid Ahmadi

Authors
  1. Mahzad Azarmehr
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  2. Majid Ahmadi
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Correspondence to Mahzad Azarmehr.

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Azarmehr, M., Ahmadi, M. Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations. Circuits Syst Signal Process 31, 2075–2091 (2012). https://doi.org/10.1007/s00034-012-9417-y

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  • DOI: https://doi.org/10.1007/s00034-012-9417-y

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