Abstract
This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinary binary number and the symmetric redundant binary number. It is implemented with the multivalued logic theory, and 3-valued and 2-valued circuits are used. The 3-valued circuit proposed in this paper is an emitter-coupled logic circuit with high speed, simplicity and powerful functions. A 3-valued ECL threshold gate can simultaneously produce six types of one-variable operations. The array multiplier, designed with the algorithm and the circuits, is fast and simple, and is suitable for building LSI. It can be used in a high-speed computer just as an ordinary binary multiplier.
Similar content being viewed by others
References
A. Avizienis, Signed-digital Number Representions for fast parallel Arithmetic,IEEE Trans. on Elec. Comp., EC-10: 9 (1961), 389–400.
A. Avizienis, A Study of Redundant Number Representions for Parallel Digital Computers, Ph.D. Thesis University of Illinois. Urbama, Illinoin, 5 (1960).
C.Y. Chow and J.E. Robwrison, Logical Design of a Redundant Binary Adder, Proc. 4th Symp. Computer Arithmetic, 10 (1978), 109–115.
N. Takagi, H. Yasuura and S. Yajima, High-speed VLSI Multiplication Algorithm with Redundant Binary Addition Tree,IEEE Trans. Comput., C-34: 9 (1985), 789–796.
Gu Weinan and Zheng Qilun, Lattice symmetric ternary logic system and its simplification,Chinese Journal of Computers,6: 4 (1983), 317–320.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Luo, Y. Algorithm and implementation of parallel multiplication in a mixed number system. J. of Comput. Sci. & Technol. 3, 203–213 (1988). https://doi.org/10.1007/BF02943345
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02943345