Formal Methods in System Design

, Volume 9, Issue 1, pp 77–104

Exploiting symmetry in temporal logic model checking


  • E. M. Clarke
    • School of Computer ScienceCarnegie Mellon University
  • R. Enders
    • Corporate Research and DevelopmentSiemens AG
  • T. Filkorn
    • Corporate Research and DevelopmentSiemens AG
  • S. Jha
    • School of Computer ScienceCarnegie Mellon University

DOI: 10.1007/BF00625969

Cite this article as:
Clarke, E.M., Enders, R., Filkorn, T. et al. Form Method Syst Des (1996) 9: 77. doi:10.1007/BF00625969


In practice, finite state concurrent systems often exhibit considerable symmetry. We investigate techniques for reducing the complexity of temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. In the past, symmetry has been exploited in computing the set of reachable states of a system when the transition relation is represented explicitly [14, 11, 19]. However, this research did not consider arbitrary temporal properties or the complications that arise when BDDs are used in such procedures.

We have formalized what it means for a finite state system to be symmetric and described techniques for reducing such systems when the transition relation is given explicitly in terms of states or symbolically as a BDD. Moreover, we have identified an important class of temporal logic formulas that are preserved under this reduction. Our paper also investigates the complexity of various critical steps, like the computation of the orbit relation, which arise when symmetry is used in this type of verification. Finally, we have tested our ideas on a simple cache-coherency protocol based on the IEEE Futurebus + standard.


model checkingsymmetrytemporal-logic
Download to read the full article text

Copyright information

© Kluwer Academic Publishers 1996