Special Section on Proofs 2013

Journal of Cryptographic Engineering

, Volume 4, Issue 3, pp 145-156

First online:

Formal verification of a software countermeasure against instruction skip attacks

  • N. MoroAffiliated withSorbonne Universités, UPMC Univ Paris 06, UMR 7606, LIP6CNRS, UMR 7606, LIP6CEA, CEA-Tech PACA, LSAS Email author 
  • , K. HeydemannAffiliated withSorbonne Universités, UPMC Univ Paris 06, UMR 7606, LIP6CNRS, UMR 7606, LIP6 Email author 
  • , E. EncrenazAffiliated withSorbonne Universités, UPMC Univ Paris 06, UMR 7606, LIP6CNRS, UMR 7606, LIP6
  • , B. RobissonAffiliated withCEA, CEA-Tech PACA, LSAS

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Abstract

Fault attacks against embedded circuits enabled to define many new attack paths against secure circuits. Every attack path relies on a specific fault model which defines the type of faults that the attacker can perform. On embedded processors, a fault model consisting in an assembly instruction skip can be very useful for an attacker and has been obtained by using several fault injection means. To avoid this threat, some countermeasure schemes which rely on temporal redundancy have been proposed. Nevertheless, double fault injection in a long enough time interval is practical and can bypass those countermeasure schemes. Some fine-grained countermeasure schemes have also been proposed for specific instructions. However, to the best of our knowledge, no approach that enables to secure a generic assembly program in order to make it fault-tolerant to instruction skip attacks has been formally proven yet. In this paper, we provide a fault-tolerant replacement sequence for almost all the instructions of the Thumb-2 instruction set and provide a formal verification for this fault tolerance. This simple transformation enables to add a reasonably good security level to an embedded program and makes practical fault injection attacks much harder to achieve.

Keywords

Microcontroller Fault attack Instruction skip Countermeasure Formal verification