Regular Paper

Journal of Cryptographic Engineering

, Volume 2, Issue 1, pp 1-18

First online:

An exploration of mechanisms for dynamic cryptographic instruction set extension

  • P. GrabherAffiliated withDepartment of Computer Science, University of Bristol Email author 
  • , J. GroßschädlAffiliated withLaboratory of Algorithmics, Cryptology and Security (LACS), University of Luxembourg
  • , S. HoerderAffiliated withDepartment of Computer Science, University of Bristol
  • , K. JärvinenAffiliated withDepartment of Information and Computer Science, Aalto University
  • , D. PageAffiliated withDepartment of Computer Science, University of Bristol
  • , S. TillichAffiliated withDepartment of Computer Science, University of Bristol
  • , M. WójcikAffiliated withDepartment of Computer Science, University of Bristol

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Abstract

Instruction set extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilise them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility”. This paper explores a new approach, namely the provision of reconfigurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

Keywords

FPGA Embedded processor Instruction set extension