Journal of Cryptographic Engineering

, Volume 2, Issue 1, pp 1–18

An exploration of mechanisms for dynamic cryptographic instruction set extension

  • P. Grabher
  • J. Großschädl
  • S. Hoerder
  • K. Järvinen
  • D. Page
  • S. Tillich
  • M. Wójcik
Regular Paper

DOI: 10.1007/s13389-011-0025-8

Cite this article as:
Grabher, P., Großschädl, J., Hoerder, S. et al. J Cryptogr Eng (2012) 2: 1. doi:10.1007/s13389-011-0025-8

Abstract

Instruction set extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilise them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility”. This paper explores a new approach, namely the provision of reconfigurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

Keywords

FPGA Embedded processor Instruction set extension 

Copyright information

© Springer-Verlag 2012

Authors and Affiliations

  • P. Grabher
    • 1
  • J. Großschädl
    • 2
  • S. Hoerder
    • 1
  • K. Järvinen
    • 3
  • D. Page
    • 1
  • S. Tillich
    • 1
  • M. Wójcik
    • 1
  1. 1.Department of Computer ScienceUniversity of BristolBristolUK
  2. 2.Laboratory of Algorithmics, Cryptology and Security (LACS)University of LuxembourgLuxembourgLuxembourg
  3. 3.Department of Information and Computer ScienceAalto UniversityAaltoFinland

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