Abstract
This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.
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Jean-Vivien Millo is currently research engineer at INRIA Sophia-Antipolis. Before, he was a researcher in the Multidisciplinary Research Lab owned by General Motors “India Science Lab” in Bangalore, India. He received his PhD degree in 2008 from University of Nice Sophia-Antipolis and his Master degree in 2005 from University of Marne-la-Vallée. Jean-Vivien Millo also got an engineering diploma in 2005 from the French ESIGETEL Engineering School.
Frédéric Mallet is currently an associate professor at University Nice Sophia Antipolis. He is a permanent member of Aoste Team-project, a joint team between INRIA Sophia Antipolis and I3S Laboratory. His work focuses on the design and analysis of real-time and embedded systems. He is one of the designers of the the Time and Allocation subprofiles of the MARTE OMG Specification.
Anthony Coadou holds a MSc degree in computer science from the University of Nice, France, and defended his PhD degree in computer science in 2010. He has been working for a year as Research Scientist with Global General Motors R&D, in Bangalore, India. His research interests include synchronous languages, formal verification and validation, and high-level synthesis and compilation.
Dr. S. Ramesh is a Lab Group Manager for the Rigorous Control Software Verification and Validation Groups at the India Science Lab, in Bangalore, which is a part of General Motors Global R&D. Ramesh has a BE (electronic & communication engineering) from Indian Institute of Science Bangalore and a PhD (computer science & engineering) from Indian Institute of Technology Bombay. He has more than 20 years of research experience in the areas of high level language design, validation and verification of distributed systems, and embedded software and hardware designs.
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Millo, JV., Mallet, F., Coadou, A. et al. Scenario-based verification in presence of variability using a synchronous approach. Front. Comput. Sci. 7, 650–672 (2013). https://doi.org/10.1007/s11704-013-3094-6
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DOI: https://doi.org/10.1007/s11704-013-3094-6