Frontiers of Computer Science

, Volume 7, Issue 5, pp 650–672

Scenario-based verification in presence of variability using a synchronous approach

  • Jean-Vivien Millo
  • Frédéric Mallet
  • Anthony Coadou
  • S. Ramesh
Research Article

DOI: 10.1007/s11704-013-3094-6

Cite this article as:
Millo, JV., Mallet, F., Coadou, A. et al. Front. Comput. Sci. (2013) 7: 650. doi:10.1007/s11704-013-3094-6
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Abstract

This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.

Keywords

Esterel UML MARTE scenario verification feature interaction variability 

Copyright information

© Higher Education Press and Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Jean-Vivien Millo
    • 1
  • Frédéric Mallet
    • 2
  • Anthony Coadou
    • 3
  • S. Ramesh
    • 3
  1. 1.INRIA Sophia-AntipolisAoste team (INRIA/I3S/CNRS/UNS)Sophia-AntipolisFrance
  2. 2.University of Nice Sophia AntipolisSophia-AntipolisFrance
  3. 3.Global General Motors R&D, India Science LabGM Technical Center IndiaBangaloreIndia

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