Article

Journal of Electronic Materials

, Volume 41, Issue 5, pp 887-894

Highly Ordered Vertical Silicon Nanowire Array Composite Thin Films for Thermoelectric Devices

  • Benjamin M. CurtinAffiliated withDepartment of Electrical and Computer Engineering, University of California Email author 
  • , Eugene W. FangAffiliated withDepartment of Electrical and Computer Engineering, University of California
  • , John E. BowersAffiliated withDepartment of Electrical and Computer Engineering, University of California

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Abstract

The fabrication and characterization of silicon nanowire (NW) array/spin-on glass (SOG) composite films for thermoelectric devices are presented. Interference lithography was used to pattern square lattice photoresist templates over entire 2 cm × 2 cm n-type Si substrates. The photoresist pattern was transferred to a SiO2 hard mask for a single-step deep reactive ion Si etch. The resulting Si NW arrays were 1 μm tall with 15% packing density, and the individual NWs had diameters of 80 nm to 90 nm with vertical sidewalls. The Si NW arrays were embedded in SOG to form a dense and robust composite material for device fabrication and thin-film characterization. The thermal conductivity of the Si NW/SOG composite film was measured to be a constant 1.45 ± 0.2 W/m-K from 300 K to 450 K. An effective medium model was then used to extract a thermal conductivity of 7.5 ± 1.7 W/m-K for the Si nanowires from the measured Si NW/SOG values. The cross-plane Seebeck coefficient of the Si NWs was measured to be −284 ± 26 μV/K, which is comparable to −310 μV/K for bulk Si. Power generation from the combined Si NW/SOG and substrate devices is also presented, and the maximum generated power was found to be 29.3 μW with ΔT of 56 K for a 50 μm × 50 μm device.

Keywords

Silicon nanowires thermoelectrics cross-plane measurements nanowire composite interference lithography power generation