Journal of Electronic Materials

, Volume 39, Issue 7, pp 1007–1014

Achieving Manufacturing Readiness for 6-Inch HgCdTe on Silicon

  • L. A. Paden
  • J. W. Bangs
  • R. M. Emerson
  • R. M. Olshove
  • E. M. Norton
  • D. A. Garnett
  • E. Smith
  • K. A. Garvine
  • J. M. Peterson
  • M. Reddy
Article

DOI: 10.1007/s11664-010-1089-4

Cite this article as:
Paden, L.A., Bangs, J.W., Emerson, R.M. et al. Journal of Elec Materi (2010) 39: 1007. doi:10.1007/s11664-010-1089-4

Six-inch HgCdTe-on-silicon wafer capability is important due to the increase in die size along with the reduction in pixel pitch. Successful manufacturing of 6-inch HgCdTe on silicon depends upon the availability of low-defect-density substrates, robust chemical processing, and in situ measuring techniques. Critical advances in wafer processing across 6-inch wafers have made the transition from development to production successful. The status of each of these steps is described in this paper, with emphasis on wafer uniformity and process reproducibility. Finally a short section is dedicated to implementation of statistical process control for optimal throughput and yield.

Keywords

HgCdTe manufacturing readiness MRL methodology large format production capability silicon MWIR 

Copyright information

© TMS 2010

Authors and Affiliations

  • L. A. Paden
    • 1
  • J. W. Bangs
    • 1
  • R. M. Emerson
    • 1
  • R. M. Olshove
    • 1
  • E. M. Norton
    • 1
  • D. A. Garnett
    • 1
  • E. Smith
    • 1
  • K. A. Garvine
    • 1
  • J. M. Peterson
    • 1
  • M. Reddy
    • 1
  1. 1.Raytheon Vision SystemsGoletaUSA

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