Journal of Electronic Materials

, Volume 34, Issue 8, pp 1104–1109

The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

  • Chihoon Lee
  • Sang Yong No
  • Da Il Eom
  • Cheol Seong Hwang
  • Hyeong Joon Kim
Regular Issue Paper

DOI: 10.1007/s11664-005-0237-8

Cite this article as:
Lee, C., No, S.Y., Eom, D.I. et al. Journal of Elec Materi (2005) 34: 1104. doi:10.1007/s11664-005-0237-8

Abstract

In order to examine the electrical and physical properties of Al2O3 layers with dual thickness on a chip, Pt gate/Al2O3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al2O3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al2O3 layers showed a good leakage current density of −5.4×10−6 A/cm2 and −2.5×10−9 A/cm2 at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×1010 cm−2eV−1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al2O3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al2O3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al2O3 layer and high reliability regions with a thick Al2O3 layer.

Key words

Si (100) metal-oxide-semiconductor (MOS) capacitors high-k gate oxide 

Copyright information

© TMS-The Minerals, Metals and Materials Society 2005

Authors and Affiliations

  • Chihoon Lee
    • 1
    • 2
  • Sang Yong No
    • 1
  • Da Il Eom
    • 1
  • Cheol Seong Hwang
    • 1
  • Hyeong Joon Kim
    • 1
  1. 1.School of Materials Science and Engineering and Inter-University Semiconductor Research CenterSeoul National UniversitySeoulKorea
  2. 2.Samsung Electronics Co., Ltd., DRAM Process Architecture TeamDevice Solution Network BusinessYongin-CityKorea

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