Transfer of semiconductor and oxide films by wafer bonding and layer cutting
- Cite this article as:
- Tong, QY., Huang, LJ. & Gösele, U.M. Journal of Elec Materi (2000) 29: 928. doi:10.1007/s11664-000-0183-4
Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to be within a temperature window that is specific for each material. The experimentally determined temperature windows for some semiconductors and single crystalline oxides will be given.