Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 243–249

Microarchitecture of the Godson-2 Processor


DOI: 10.1007/s11390-005-0243-6

Cite this article as:
Hu, WW., Zhang, FX. & Li, ZS. J Comput Sci Technol (2005) 20: 243. doi:10.1007/s11390-005-0243-6


The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.


superscalar pipelineout-of-order executionbranch predictionregister renamingdynamic scheduling non-blocking cacheload speculation

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Institute of Computing TechnologyChinese Academy of SciencesBeijingP.R. China