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3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation

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Abstract

This paper presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmentation is performed using Expectation-Maximization (EM) with Maximization of Posterior Marginals (MPM) Bayesian algorithm. This algorithm segments the 3D image using neighboring pixels based on a Markov Random Field (MRF) model. In this system, the embedded processor controls a custom circuit which performs the MPM and portions of the EM algorithm. The embedded processor completes the EM algorithm and also controls image data transmission between host computer and on-board memory. The whole system has been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times processing improvement compared to standard desktop computer. Three new techniques were the key to achieve this speed: Pipelined computational cores, sixteen parallel data paths and a novel memory interface for maximizing the external memory bandwidth.

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Correspondence to Lauren Christopher.

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Liu, C., Sun, Y. & Christopher, L. 3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation. J Sign Process Syst 81, 411–424 (2015). https://doi.org/10.1007/s11265-014-0965-1

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  • DOI: https://doi.org/10.1007/s11265-014-0965-1

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