Journal of Signal Processing Systems

, Volume 66, Issue 3, pp 285–301

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

Authors

    • National Instruments Corp.
  • Chung-Ching Shen
    • Department of ECE and UMIACSUniversity of Maryland
  • Shuvra S. Bhattacharyya
    • Department of ECE and UMIACSUniversity of Maryland
  • Ian Wong
    • National Instruments Corp.
  • Yong Rao
    • National Instruments Corp.
  • Jacob Kornerup
    • National Instruments Corp.
Article

DOI: 10.1007/s11265-011-0599-5

Cite this article as:
Kee, H., Shen, C., Bhattacharyya, S.S. et al. J Sign Process Syst (2012) 66: 285. doi:10.1007/s11265-011-0599-5

Abstract

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

Keywords

Dataflow modelingSchedulingFPGA implementation4G communication systemsParameterized dataflow

Copyright information

© Springer Science+Business Media, LLC 2011