Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
- Hojin KeeAffiliated withNational Instruments Corp. Email author
- , Chung-Ching ShenAffiliated withDepartment of ECE and UMIACS, University of Maryland
- , Shuvra S. BhattacharyyaAffiliated withDepartment of ECE and UMIACS, University of Maryland
- , Ian WongAffiliated withNational Instruments Corp.
- , Yong RaoAffiliated withNational Instruments Corp.
- , Jacob KornerupAffiliated withNational Instruments Corp.
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In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.
KeywordsDataflow modeling Scheduling FPGA implementation 4G communication systems Parameterized dataflow
- Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Journal of Signal Processing Systems
Volume 66, Issue 3 , pp 285-301
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- Springer US
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- Dataflow modeling
- FPGA implementation
- 4G communication systems
- Parameterized dataflow
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