Journal of Signal Processing Systems

, Volume 57, Issue 3, pp 331-338

First online:

Low-Power Multiplier Design Using a Bypassing Technique

  • Chua-Chin WangAffiliated withDepartment of Electrical Engineering, National Sun Yat-Sen University Email author 
  • , Gang-Neng SungAffiliated withDepartment of Electrical Engineering, National Sun Yat-Sen University

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This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads’ power dissipation compared to the prior works.


Low power multiplier Bypassing Partial product Timing control