, Volume 57, Issue 3, pp 331-338
Date: 04 Dec 2008

Low-Power Multiplier Design Using a Bypassing Technique

Rent the article at a discount

Rent now

* Final gross prices may vary according to local VAT.

Get Access

Abstract

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads’ power dissipation compared to the prior works.

This research was partially supported by National Science Council under grant NSC96-2628-E-110-018-MY3 and National Health Research Institutes under grant NHRI-EX97-9732EI.