Low-Power Multiplier Design Using a Bypassing Technique
Purchase on Springer.com
$39.95 / €34.95 / £29.95*
Rent the article at a discountRent now
* Final gross prices may vary according to local VAT.
This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads’ power dissipation compared to the prior works.
- Choi, J., Jeon, J., & Choi, K. (2000). Power minimization of functional units by partially guarded computation. In 2000 International symposium on low power electronics and design (ISLPED’00) pp. 131–136, July.
- Di, J., Yuan, J. S., & Hagedorn, M. (2002). Energy-aware multiplier design in multi-rail encoding logic. In The 2002 45th Midwest symposium on circuits and systems (MWSCAS-2002) (Vol. 2, pp. 294–297), Aug.
- Hwang, W., Gristede, G. D., Sanda, P. N., Wang, S. Y., & Heidel, D. F. (1999). Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. IEEE Journal of Solid-State Circuits, 34(8), 1108–1117. CrossRef
- Hong, S., Kim, S., Papaefthymiou, M. C., & Stark, W. E. (1999). Low power parallel multiplier design for DSP applications through coefficient optimization. In 1999 twelfth annual IEEE international ASIC/SOC conference pp. 286–290, Sep.
- Ohban, J., Moshnyaga, V. G., & Inoue, K. (2002). Multiplier energy reduction through bypassing of partial products. In 2002 Asia-Pacific conference on circuits and systems (APCCAS ’02) (Vol. 2, pp. 13–17), Oct.
- Ahn, T., & Choi, K. (1997). Dynamic operand interchange for low power. Electronics Letters, 33(25), 2118–2120. CrossRef
- Shen, N.-Y., & Chen, O. T.-C. (2002). Low-power multipliers by minimizing switching activities of partial products. In IEEE international symposium on circuits and systems, 2002 (ISCAS 2002) (Vol. 4, pp. IV-93-IV-96), May.
- Wang, C.-C., Huang, C.-J., & Tsai, K.-C. (2000). A 1.0 GHz 0.6-μm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic. IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 47(2), 133–135, Feb.
- Kang, J.-Y., & Gaudiot, J.-L. (2006) A simple high-speed multiplier design. IEEE Transactions on Computers, 55(10), 1253–1258. CrossRef
- Wang, C.-C., Tseng, Y.-L., Lee, P.-M., Lee, R.-C., & Huang, C.-J. (2003). A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic. IEEE Transactions on Circuits and Systems—I Fundamental Theory and Applications, 50(9), 1208–1216. CrossRef
- Islam, F. F., & Tamaru, K. (1995). High speed merged array multiplication. The Journal of VLSI Signal Processing Systems for Signal, Image, and Technology, 10(1), 41–52. CrossRef
- Low-Power Multiplier Design Using a Bypassing Technique
Journal of Signal Processing Systems
Volume 57, Issue 3 , pp 331-338
- Cover Date
- Print ISSN
- Online ISSN
- Springer US
- Additional Links
- Low power multiplier
- Partial product
- Timing control
- Industry Sectors