Skip to main content
Log in

Realizing frequently used permutations on gamma interconnection network’s family networks with the help of alternate source

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

This paper proposes a new variant of Gamma Interconnection Network (GIN), which uses an alternate source at the initial stage. The alternate source helped in realizing the Bit Reversal permutation completely in one pass. The paper also proposes a modified permutation realization algorithm, which is being used to realize the frequently used permutations on GIN family of networks. This algorithm also ensures that the alternate source approach can be used with all the GIN family networks with sizes \(\ge \)8 to realize the frequently used permutations. The paper also discusses the performance of the modified algorithm in terms of hop count required to realize the permutations as well as the effect on hardware cost due to alternate source.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Advanced Computer Architecture, Kai Hwang, Tata–McGraw Hill Publications

  2. Interconnection networks, William J. Dally, Morgan–Kaufmann Publication

  3. Ananth G, Anshul G, George K, Vipin K, Addison W. An Introduction to Parallel Computing

  4. Barry W. Parallel programming, Pearson Education

  5. Feng TY (1981) A survey of interconnection metworks. IEEE Transactions on Computers (December 1981)

  6. Adams III GB, Agrawal DP, Siegel HJ (1987) A survey and comparison of Fault–Tolerant Multistage Interconnection Networks. IEEE Transactions on Computers

  7. Parker DS, Raghavendra CS (1982) The gamma network: a multiprocessor interconnection network with redundant paths. IEEE Transactions on Computers, Los Alamitos

  8. Parker DS, Raghavendra CS (1984) The gamma network. IEEE Transactions on Computers c–33(4)

  9. Kothari SC, Prabhu GM, Roberts Robert (1988) The kappa network with fault–tolerant destination tag algorithm. IEEE Transactions On Computers 37(5)

  10. Lee KY, Hegazy W (1988) The extra stage gamma network. IEEE Transactions on Computer 37(11)

  11. Lee KY, Yoon H (1990) The B–Network: A Multistage Interconnection Network With Backward Links. IEEE Transactions on Computer 39(7), July 1990

  12. Venkatesan R, Mouftah HT (1992) Balanced gamma network-a new candidate for broadband packet switch architectures. IEEE Transactions on Computer, INFOCOM

  13. Chen CW, Lu NP, Chen TF, Chung CP (2000) Fault tolerant gamma interconnection networks by chaining. IEE Proceedings—Comput. Digit. Tech 147(2)

  14. Chuang PJ (1998) Creating a highly reliable modified gamma interconnection network using a balance approach. IEE Proceedings—Comput. Digit. Tech 145(1)

  15. Tzeng NF, Chuang PJ, Wu CH (1993) Creating disjoint Ppaths in gamma interconnection networks. IEEE Trans Comp 42(10)

  16. Chuang PJ (1994) CGIN: a modified gamma interconnection network with multiple disjoint paths. IEEE Trans Comp

  17. Chen CW, Lu NP, Chung CP (2003) 3-Disjoint gamma interconnection network. J Syst Software

  18. Rau D, Fortes Jose AB, Siegel HJ (1992) Destination tag routing techniques based on a stage model for the IADM network. IEEE Trans Comp 42(3)

  19. Chen CW, Ku CJ, Chang CH (2005) Design schemes and performance analysis of dynamic rerouting interconnection networks for tolerating faults and preventing collisions. Parallel and Distributed Processing and Applications, ISPA

  20. Chen Zhen, A Class of Incomplete Gamma Interconnection Network. Available at: www.researchgate.com

  21. Borkar MA (2010) A survey of fault tolerance techniques used in GIN. in National Conference EEC

  22. Borkar MA, Nitin (2011) 3D–CGIN: a 3 disjoint paths CGIN with alternate source. In: ACC

  23. Barlik PK (2011) FIR filter IC design using redundant binary number systems. M.Tech Thesis, NIT Rourkela, India

  24. Borkar Meenal A (2011) 3D–CGIN: a 3Disjoint paths CGIN with alternate source. M.Tech Dissertation, UTU Dehradun, India

  25. Borkar Meenal A, Nitin (2012) Network status aware routing in 3D–CGIN. In: ICCCS

  26. Varma A, Raghavendra CS (1986) On permutations passable by the gamma network. J Parall Distrib Comp 3

  27. Sharma S (2012) On permutation capabilities of fault tolerant multistage interconnection networks. IJCSI 9(6):3

  28. Borkar Meenal A, Bhadana B (2014) On performance evaluation parameters of multistage interconnection networks. In Second ICSET. Ansal University, Gurgaon, India

  29. Avizienis A (1961) Signed–digit number representations for fast parallel arithmetic. IRE Trans, EC–10

  30. Interconnection Networks: an engineering approach, J Duato, Morgan–Kaufmann Publication

  31. Chaoyang CQ, A minimal cost dynamic rerouting gamma network. Available at: www.cyut.edu.tw

  32. Rajkumar S, Goyal Neeraj K (2014) Design of 4–disjoint gamma interconnection layouts and reliability analysis of gamma interconnection networks. J Supercomp

  33. Chen CW, Chung CP (2001) Fault tolerant gamma interconnection networks without backtracking. J Syst Software

  34. Nitin, Vaish R, Srivastava U (2010) On a deadlock and performance analysis of ALBR and DAR algorithm on X-torus topology by optimal utilization of cross links and minimal lookups. J Supercomp Springer 59(3):1252–1288

  35. Nitin, Chauhan DS (2010) Stochastic communication for application specific networks-on-chip. J Supercomp Springer 59(2):779–810

  36. Nitin, Durg SC (2010) Comparative analysis of traffic patterns on k-ary n-tree using adaptive algorithms based on burton normal form. J Supercomp Springer 59(2):569–588

  37. Nitin R, Nitin (2010) Analysis of multi-sort algorithm on multi-mesh of trees (MMT) architecture. J Supercomp Springer 57(3):276–313

  38. Nitin, Garhwal S, Srivastava N (2009) Designing a fault-tolerant fully-chained combining switches multi-stage interconnection network with disjoint paths. J Supercomp Springer 55(3):400–431

  39. Arabnia HR (1995) A Distributed Stereo correlation Algorithm, Proceedings of Computer Communications and Networks (ICCCN’95). IEEE pp 479–482

  40. Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parall Comp (J) Elsevier 21(11):1783–1806

    Article  Google Scholar 

  41. Arabnia HR, Smith JW (1993) A Reconfigurable Interconnection Network For Imaging Operations And Its Implementation Using A Multi-Stage Switching Box, Proceedings of the 7th Annual International High Performance Computing Conference. The 1993 High Performance Computing: New Horizons Supercomputing Symposium, Calgary, Alberta, Canada, pp 349–357

  42. Arif Wani M, Arabnia HR (2003) Parallel Edge-Region-Based Segmentation Algorithm Targeted at Reconfigurable Multi-Ring Network. J Supercomp 25(1):43–63

    Article  MATH  Google Scholar 

  43. Arabnia HR (1990) A Parallel Algorithm for the Arbitrary Rotation of Digitized Images using Process-and-Data-Decomposition Approach. J Parall Distrib Comp 10(2):188–193

    Article  Google Scholar 

  44. Arabnia HR, Oliver MA (1989) A transputer network for fast operations on digitised images. Int J Euro Assoc (Comp Graph Forum) 8(1):3–12

    Google Scholar 

  45. Bhandarkar SM, Arabnia HR (1995) The though transform on a reconfigurable multi-ring network. J Parall Distrib Comp 24(1):107–114

    Article  Google Scholar 

  46. Arabnia HR, Oliver MA (1987) A transputer network for the arbitrary rotation of digitized images. Comp J 30(5):425–433

    Article  Google Scholar 

  47. Arabnia HR, Bhandarkar SM (1996) Parallel Stereo correlation on a Reconfigurable Multi-Ring Network. J Supercomp (Springer Publishers) 10(3):243–270

    Article  MATH  Google Scholar 

  48. Arabnia HR, Oliver MA (1987) Arbitrary Rotation of Raster Images with SIMD Machine Architectures. Int J Euro Assoc (Computer Graphics Forum) 6(1):3–12

    Google Scholar 

  49. Bhandarkar SM, Arabnia HR, Smith JW (1995) A Reconfigurable Architecture For Image Processing And Computer Vision, International Journal of Pattern Recognition And Artificial Intelligence (IJPRAI) (special issue on VLSI Algorithms and Architectures for Computer Vision, Image Processing, Pattern Recognition And AI) 9(2):201–229

Download references

Conflict of interest

The authors declare that they have no conflict of interest.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Nitin.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Borkar, M., Nitin Realizing frequently used permutations on gamma interconnection network’s family networks with the help of alternate source. J Supercomput 71, 4327–4351 (2015). https://doi.org/10.1007/s11227-015-1527-4

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-015-1527-4

Keywords

Navigation