Skip to main content
SpringerLink
Log in

An analytical method for reliability aware instruction set extension

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Random variations and low reliability of nanometer new silicons are the most important concerns for the fault-tolerant design of large-area powerful integrated circuits. Logic faults in terms of soft errors or transient faults are now serious problems for embedded processing cores. Recently, augmenting an embedded processor with application specific custom instructions is widely used for improving the performance of a processor. Although area, power, and performance of an augmented processor have been considered for efficient custom instruction selection, its reliability consideration is much needed. This is impeding because this action needs exhaustive fault injection and lengthy and expensive simulations. This demand becomes more serious in the case of many-core, larger area and, therefore, more fault-prone integrated circuits, e.g., tera-computing processors. In this work, we propose an analytical modeling solution for such a demanding problem. First, a simple analytical method is introduced that can evaluate the vulnerability of a custom instruction in a time-saving manner. Using this method and our configurable custom instruction vulnerability analysis framework, the effects of type, order, and word length of various operations of different custom instruction subgraphs on the vulnerability of an extensible processor have been explored analytically and experimentally. Based on our results, for example, replacing orders of operators in custom functional units could yield different vulnerabilities to soft errors. Therefore, our approach enables designers to optionally constrain the operand types and also the custom functional unit structures to reach an acceptable vulnerability level at low computational and design time costs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Asadi G, Tahoori M (2005) An analytical approach for soft error rate estimation in digital circuits. In: IEEE International Symposium on Circuits and Systems, ISCAS 2005, vol 3, pp 2991–2994. doi:10.1109/ISCAS.2005.1465256

    Chapter  Google Scholar 

  2. Asadi H, Tahoori M (2007) Analytical techniques for soft error rate modeling and mitigation of fpga-based designs. IEEE Trans Very Large Scale Integr (VLSI) Syst 15(12):1320–1331. doi:10.1109/TVLSI.2007.909795

    Article  Google Scholar 

  3. Atasu K, Luk W, Mencer O, Ozturan C, Dundar G (2012) Fish: fast instruction synthesis for custom processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(1):52–65. doi:10.1109/TVLSI.2010.2090543

    Article  Google Scholar 

  4. Azarpeyvand A, Salehi M, Fakhraie S (2012) Civa: custom instruction vulnerability analysis framework. In: IEEE 15th international symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp 318–323. doi:10.1109/DDECS.2012.6219081

    Google Scholar 

  5. Azarpeyvand A, Salehi M, Fakhraie S (2012) Vulnerability analysis for custom instructions. In: 15th euromicro conference on Digital System Design (DSD), pp 144–147. doi:10.1109/DSD.2012.139

    Google Scholar 

  6. Azarpeyvand A, Salehi M, Firouzi F, Yazdanbakhsh A, Fakhraie SM (2010) Instruction reliability analysis for embedded processors. In: IEEE 13th international symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp 20–23. doi:10.1109/DDECS.2010.5491824

    Chapter  Google Scholar 

  7. Bordoloi U, Tanasa B, Tahoori M, Eles P, Peng Z, Shazli S, Chakraborty S (2012) Reliability-aware instruction set customization for asips with hardened logic. In: IEEE 18th international conference on embedded and Real-Time Computing Systems and Applications (RTCSA), pp 164–173. doi:10.1109/RTCSA.2012.28

    Google Scholar 

  8. Borodin D, Juurlink BH (2010) Protective redundancy overhead reduction using instruction vulnerability factor. In: Proceedings of the 7th ACM international conference on computing frontiers, CF’10. ACM, New York, pp 319–326. doi:10.1145/1787275.1787342

    Google Scholar 

  9. Brisk P, Kaplan A, Sarrafzadeh M (2004) Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. In: Proceedings. 41st, Design Automation Conference, pp 395–400

    Google Scholar 

  10. Fazeli M, Miremadi S, Asadi H, Tahoori M (2010) A fast analytical approach to multi-cycle soft error rate estimation of sequential circuits. In: 13th euromicro conference on Digital System Design: architectures, methods and tools (DSD), pp 797–800. doi:10.1109/DSD.2010.74

    Google Scholar 

  11. Gonzalez R (2000) Xtensa: a configurable and extensible processor. IEEE MICRO 20(2):60–70. doi:10.1109/40.848473

    Article  Google Scholar 

  12. Ienne P (2006) Customizable embedded processors: design technologies and applications. Elsevier, San Diego

    Google Scholar 

  13. Jones T, O’Boyle M, Ergin O (2008) Evaluating the effects of compiler optimisations on avf. In: 12th annual workshop on the interaction between compilers and computer architecture (INTERACT) in conjunction with HPCA-14

    Google Scholar 

  14. Lam SK, Srikanthan T (2009) Rapid design of area-efficient custom instructions for reconfigurable embedded processing. J Syst Archit 55(1):1–14. doi:10.1016/j.sysarc.2008.06.003

    Article  Google Scholar 

  15. Lam SK, Srikanthan T, Clarke C (2011) Architecture-aware technique for mapping area-time efficient custom instructions onto fpgas. IEEE Trans Comput 60(5):680–692. doi:10.1109/TC.2010.237

    Article  MathSciNet  Google Scholar 

  16. Martin G (2006) Recent developments in configurable and extensible processors. In: International conference on Application-specific Systems, Architectures and processors, ASAP’06, pp 39–44. doi:10.1109/ASAP.2006.57

    Google Scholar 

  17. Moreano N, Borin E, de Souza C, Araujo G (2005) Efficient datapath merging for partially reconfigurable architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(7):969–980. doi:10.1109/TCAD.2005.850844

    Article  Google Scholar 

  18. Mukherjee SS, Weaver C, Emer J, Reinhardt SK, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In: Proceedings of the 36th annual IEEE/ACM international symposium on microarchitecture. MICRO, vol 36. IEEE Comput. Soc., Washington, p 29

    Google Scholar 

  19. Papoulis A, Pillai S (2002) Probability, random variables, and stochastic processes. McGraw–Hill series in electrical and computer engineering. McGraw-Hill, New York

    Google Scholar 

  20. Parker K, McCluskey E (1975) Probabilistic treatment of general combinational networks. IEEE Trans Comput C-24(6):668–670. doi:10.1109/T-C.1975.224279

    Article  MathSciNet  Google Scholar 

  21. Rehman S, Shafique M, Henkel J (2012) Instruction scheduling for reliability-aware compilation. In: Proceedings of the 49th annual Design Automation Conference, DAC’12. ACM, New York, pp 1292–1300. doi:10.1145/2228360.2228601

    Chapter  Google Scholar 

  22. Rehman S, Shafique M, Kriebel F, Henkel J (2011) Reliable software for unreliable hardware: embedded code generation aiming at reliability. In: Proceedings of the seventh IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS’11. ACM, New York, pp 237–246. doi:10.1145/2039370.2039408

    Chapter  Google Scholar 

  23. Reis GA, Chang J, August DI (2007) Automatic instruction-level software-only recovery. IEEE MICRO 27(1):36–47. doi:10.1109/MM.2007.4

    Article  Google Scholar 

  24. Seto K, Fujita M (2008) Custom instruction generation with high-level synthesis. In: Symposium on Application Specific Processors, SASP 2008, pp 14–19. doi:10.1109/SASP.2008.4570780

    Chapter  Google Scholar 

  25. Shivakumar P, Kistler M, Keckler S, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings. international conference on Dependable Systems and Networks, DSN 2002, pp 389–398. doi:10.1109/DSN.2002.1028924

    Google Scholar 

  26. Wang F, Xie Y (2011) Soft error rate analysis for combinational logic using an accurate electrical masking model. IEEE Trans Dependable Secure Comput 8(1):137–146. doi:10.1109/TDSC.2009.29

    Article  MathSciNet  Google Scholar 

  27. Wang Z, Jiang J, Yang G (2007) Implementation and analysis of probabilistic methods for gate-level circuit reliability estimation. Tsinghua Sci Technol 12(S1):32–38. doi:10.1016/S1007-0214(07)70080-9

    Article  MathSciNet  Google Scholar 

  28. Zhang Y, Chakrabarty K, Swaminathan V (2003) Energy-aware fault tolerance in fixed-priority real-time embedded systems. In: International Conference on Computer Aided Design, ICCAD-2003, pp 209–213. doi:10.1109/ICCAD.2003.1257640

    Google Scholar 

  29. Ziegler JF, Curtis HW, Muhlfeld HP, Montrose CJ, Chin B, Nicewicz M, Russell CA, Wang WY, Freeman LB, Hosier P, LaFave LE, Walsh JL, Orro JM, Unger GJ, Ross JM, O’Gorman TJ, Messina B, Sullivan TD, Sykes AJ, Yourke H, Enger TA, Tolat V, Scott TS, Taber AH, Sussman RJ, Klein WA, Wahaus CW (1996) Ibm experiments in soft fails in computer electronics (1978–1994). IBM J Res Dev 40(1):3–18. doi:10.1147/rd.401.0003

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, North Kargar Ave., Tehran, 14395-515, Islamic Republic of Iran

    Ali Azarpeyvand, Mostafa E. Salehi & Sied Mehdi Fakhraie

  2. Electrical an Computer Engineering Department, University of Zanjan, Zanjan, Iran

    Ali Azarpeyvand

Authors
  1. Ali Azarpeyvand
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Mostafa E. Salehi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Sied Mehdi Fakhraie
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sied Mehdi Fakhraie.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Azarpeyvand, A., Salehi, M.E. & Fakhraie, S.M. An analytical method for reliability aware instruction set extension. J Supercomput 67, 104–130 (2014). https://doi.org/10.1007/s11227-013-0990-z

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-013-0990-z

Keywords

Search

Navigation