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High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study

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Abstract

Technological advancements in the silicon industry, as predicted by Moore’s law, have resulted in an increasing number of processor cores on a single chip, giving rise to multicore, and subsequently many-core architectures. This work focuses on identifying key architecture and software optimizations to attain high performance from tiled many-core architectures (TMAs)—an architectural innovation in the multicore technology. Although embedded systems design is traditionally power-centric, there has been a recent shift toward high-performance embedded computing due to the proliferation of compute-intensive embedded applications. The TMAs are suitable for these embedded applications due to low-power design features in many of these TMAs. We discuss the performance optimizations on a single tile (processor core) as well as parallel performance optimizations, such as application decomposition, cache locality, tile locality, memory balancing, and horizontal communication for TMAs. We elaborate compiler-based optimizations that are applicable to TMAs, such as function inlining, loop unrolling, and feedback-based optimizations. We present a case study with optimized dense matrix multiplication algorithms for Tilera’s TILEPro64 to experimentally demonstrate the performance and performance per watt optimizations on TMAs. Our results quantify the effectiveness of algorithmic choices, cache blocking, compiler optimizations, and horizontal communication in attaining high performance and performance per watt on TMAs.

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Acknowledgements

This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC), the Space and Naval Warfare Systems Command (SPAWAR N66001-11-1-4103), the Office of Naval Research (ONR R16480), and the National Science Foundation (NSF) (CNS-0953447 and CNS-0905308). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSERC, the SPAWAR, the ONR, and the NSF. Furthermore, the views expressed are those of the author(s) and do not reflect the official policy or position of the Department of Defense or the US Government. We would like to acknowledge Dr. Alan D. George, Director of the NSF Center of High-Performance Reconfigurable Computing (CHREC) at the University of Florida, Gainesville, Florida, USA, for providing access to CHREC resources and Tilera’s TILE64 and TILEPro64 for this work as well as discussions on high-performance computing with the leading author of this article.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA

    Arslan Munir & Farinaz Koushanfar

  2. Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA

    Ann Gordon-Ross

  3. NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida, Gainesville, FL, USA

    Ann Gordon-Ross

  4. Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA

    Sanjay Ranka

Authors
  1. Arslan Munir
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  2. Farinaz Koushanfar
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  3. Ann Gordon-Ross
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  4. Sanjay Ranka
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Corresponding author

Correspondence to Arslan Munir.

Appendix: Matrix multiplication algorithms’ code snippets for Tilera’s TILEPro64

Appendix: Matrix multiplication algorithms’ code snippets for Tilera’s TILEPro64

This appendix section provides code snippets of our matrix multiplication algorithms for Tilera’s TILEPro64. The code snippets are presented selectively to provide an understanding of our algorithms and some portions of the code are skipped for conciseness.

1.1 A.1 Serial non-blocked matrix multiplication algorithm

1.1.1 A.1.1 SerialNonBlockedMM.h

figure a

1.1.2 A.1.2 SerialNonBlockedMM.c

figure b

1.2 A.2 Serial blocked matrix multiplication algorithm

1.2.1 A.2.1 SerialBlockedMM.h

figure c

1.2.2 A.2.2 SerialBlockedMM.c

figure d

1.3 A.3 Parallel blocked matrix multiplication algorithm

1.3.1 A.3.1 ParallelBlockedMM.h

figure e

1.3.2 A.3.2 ParallelBlockedMM.c

figure f

1.4 A.4 Parallel blocked cannon’s algorithm for matrix multiplication

1.4.1 A.4.1 ParallelBlockedCannonMM.h

figure g

1.4.2 A.4.2 ParallelBlockedCannonMM.c

figure h

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Munir, A., Koushanfar, F., Gordon-Ross, A. et al. High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study. J Supercomput 66, 431–487 (2013). https://doi.org/10.1007/s11227-013-0916-9

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