Hybrid silicon integration
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- Cite this article as:
- Jones, R., Park, H.D., Fang, A.W. et al. J Mater Sci: Mater Electron (2009) 20: 3. doi:10.1007/s10854-007-9418-y
An overview is presented of the hybrid AlGaInAs-silicon platform that enables wafer level integration of III-V optoelectronic devices with silicon photonic devices based on silicon-on-insulator (SOI). Wafer bonding AlGaInAs quantum wells to an SOI wafer allows large scale hybrid integration without any critical alignment steps. Discrete hybrid silicon optical amplifiers, lasers and photodetectors are described, and the integration of a ring laser with on-chip and photo-detector and amplified spontaneous emission (ASE) seed to enable unidirectional lasing.
Silicon photonics has the potential to provide highly integrated, low-cost, optical components using the same CMOS-based manufacturing techniques that revolutionized the micro-electronics industry. This is important as lowering the cost of optical interconnects would enable high-bandwidth optical communication links in and around personal computers and servers where their cost today is prohibitively expensive. Silicon has many properties that make it ideal as a material for integrated optics. Silicon’s band edge at 1.1 μm makes it compatible with long wavelength infra-red communication links, its high refractive index contrast with its native oxide (Δn ∼2) enables small-footprint integrated optical devices, and of course high volume manufacturing techniques can be used to fabricate silicon photonic chips at low cost [1, 2].
Both passive and active photonic devices have been demonstrated built on silicon-on-insulator (SOI) substrates such as WDM splitters for fiber to the home applications  and high speed optical modulators . As silicon is transparent above 1.1 μm it cannot be used as a photo-detector in the 1.31 μm and 1.55 μm communication windows but other CMOS compatible group IV materials have been suggested for this role, e.g. germanium . The key issue for material compatibility is the ability to process devices on the same SOI wafer as other silicon components simultaneously across the wafer. In fact all the devices needed for an optical link can be fabricated from silicon or compatible materials apart from the laser. Due to silicon’s indirect band gap light emission is very inefficient  and currently the preferred method of integrating lasers with silicon chips is to align and then attach individual prefabricated lasers to silicon waveguides one at a time. This has the key drawback that the assembly time increases as the required number of lasers increases. Consider, for example, a typical 6-inch SOI wafer containing 44 silicon die each requiring eight lasers, individually attaching 352 lasers to each wafer is clearly not a time- or cost-efficient solution. A better approach would be to use the same wafer-scale fabrication techniques to manufacture both the silicon photonic components and the laser. That is the aim of the hybrid laser work discussed here.
2 Hybrid silicon device architecture
The hybrid-silicon platform allows silicon photonic devices to be integrated with active optoelectronic devices more commonly associated with III–V materials such as: electrically pumped lasers; amplifiers; wavelength converters; and photo-detectors.
Epitaxial structure of InP wafer
P contact layer
P-type ln0.53 Ga0.47 As
1 × 1019 cm–3
1 × 1018 cm–3
Separate Confinement Heterostructure
P-type Al0.131Ga0.34As,1.3 μm
1 × 1017 cm–3
Al0.089Ga0.461ln0.45As, 1.3 μm (9x)
Al0.055Ga0.292ln0.653As, 1.7 μm (8x)
1 × 1018 cm–3
N-type ln0.85Ga0.15ln0.653As0.327P0.673 (2x)
1 × 1018 cm–3
1 × 1018 cm–3
N bonding layer
1 × 1018 cm–3
3 Device fabrication
Fabry–Perot lasers at 1326 nm  and 1577 nm  have been fabricated using this hybrid waveguide architecture as well as optical amplifiers , photodetectors  and ring lasers . The generic device process flow is as follows.
First waveguides are patterned on the (100) surface of an undoped SOI substrate with a 1 μm thick buried oxide layer using standard projection photolithography and Cl2/Ar/HBr- based plasma reactive ion etching. These waveguides may include passive components such as optical (de)multiplexers, or ring resonators or simply straight waveguides used to demonstrate Fabry–Perot lasers.
Next the InP wafer and the SOI wafer undergo a rigorous surface clean, oxygen plasma surface treatment, and wash in deionised water prior to bonding. During the plasma treatment a thin hydrophilic (<5 nm) oxide layer is grown on the surface of each wafer which is then terminated by highly reactive polar hydroxyl groups during the deionised water dip. When the two wafers are subsequently placed together the hydroxyl groups form bridging bonds between the two surfaces resulting in weak spontaneous bonding of the two wafers. To enhance the strength of this spontaneous bond the wafer are then placed in an annealing chamber at 300 °C at a pressure of 2 MPa for 12 h. This slow bake helps out diffusion of interface trapped molecules and activates the formation of stronger covalent bonds, resulting in stronger bonding of the two materials. After bonding the InP is patterned into mesa’s; the N- and P-metals are deposited followed by proton implantation of the mesa to form a conductive channel in the center of the mesa through which current can flow. A typical hybrid silicon active cross-section is shown in Fig 1. More details of device fabrication are given in [7–11].
3.1 Hybrid silicon amplifiers
3.2 Hybrid silicon lasers
Of course demonstrating net gain allows one to fabricate a laser. Both Fabry–Perot and ring lasers have demonstrated using this hybrid platform, at both 1326 nm and 1577 nm wavelength. 1577 nm Fabry–Perot lasers have been fabricated from hybrid waveguides polished to a length of 850 μm [7, 8]. Again coupling from the laser was done using lensed fiber with a coupling loss of 6 dB to the hybrid waveguides with silicon dimensions of 2.5 μm, 0.76 μm and for the silicon strip waveguide width and height. The mode overlap with the silicon waveguide and quantum wells is calculated to be 75% and 3% respectively. The hybrid waveguide facets were polished to give ∼30% reflectivity end mirrors.
3.3 Hybrid silicon photodetectors
3.4 Integrated hybrid silicon chip
In general ring lasers suffer from bi-directional lasing, that is lasing occurs in the clockwise and anti-clockwise direction in the ring . Coupling between the degenerate clockwise and anti-clockwise modes results in instability and kinks in the L–I curve of the single sided laser output, see for example the dotted grey curve in Fig. 10. One way to force unidirectional lasing is to seed the cavity in the preferred direction with an external light source. Here we integrate an ASE seed with the ring laser to obtain unidirectional lasing and an on-chip power monitor to ease device testing using the hybrid silicon platform.
The responsivity of the photodetectors was measured by dicing and polishing a discrete detector in the same chip and launching laser light into the detector through a lensed fiber. The fiber coupled responsivity was measured to be 0.25 A/W at 1580 nm. Taking into consideration the ∼30% reflection off the waveguide facet and an estimated 5.25 ± .25 dB coupling loss, we estimate the photodetector responsivity to be in the range of 1.25–1.11 A/W. This corresponds to a quantum efficiency between 97–86%. We use a responsivity of 1.25 A/W in the remainder of this section such that the laser power values are on the conservative side. The detector dark current was measured to be 200 μA.
4 Wafer level processing
Wafer to wafer bonding: here bonding would be done using whole InP wafers, which has the advantage that the surface treatment and bonding is done on a complete III–V wafer easing the handling. Disadvantages include the disparity between commercially available SOI and InP wafers. 12-inch SOI wafers are readily available whereas InP wafers are only now becoming available at 6-inch size, although at high cost. Obviously this disparity in size of the available wafers reduces the attractiveness of this approach as it does not allow the full usage, and hence economics of the large SOI wafers.
Given that a significant amount of the III–V wafer will be etched away during device fabrication a better approach might be bonding multiple III–V die to an SOI wafer. This has the key advantage that scaling can be done to any SOI wafer size irrespective of the III–V wafer availability, and the III–V die size can be set to efficiently use the InP material. All this comes at the cost of processing complexity, as every die needs to undergo its own surface treatment before bonding, followed by rough alignment of the die to SOI wafer. However, in general the economic advantages of being able to buy smaller III–V wafers to process large SOI wafers makes this approach more attractive.
The hybrid silicon platform is described which can be used to integrated III–V optoelectronic components with silicon photonics. The novelty of this approach lies in the wafer scale fabrication it opens up for lasers and other active devices on a silicon platform. Amplifiers with 13 dB on-chip gain, photo-detectors with 90% quantum efficiency and lasers with output powers of 14 mW are described. As proof of the integration potential of this platform a unidirectional laser is presented by integrating an ASE seed with a ring laser and on-chip power monitor. This wafer scale approach to integration of active components onto silicon will enable optical interconnects around PC’s and servers where their current price is too expensive.
This work was supported by DARPA through contracts W911NF-05-1-0175 and W911NF-04-9-0001, and by Intel. The authors thank Jag Shah, Mike Haney, Matt Sysak, Ying-Hao Kuo, Di Liang, Brian Koch and Emily Burmeister for useful discussions and K. Callegari and G. Zeng for sample preparation.