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On the Simulation of HCI-Induced Variations of IC Timings at High Level

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Abstract

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.

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Authors and Affiliations

  1. CEA, LIST, Embedded Computing Laboratory, PC172, 91191, Gif-sur-Yvette Cedex, France

    Olivier Heron, Clement Bertolini, Chiara Sandionigi & Nicolas Ventroux

  2. Universite Bordeaux 1, ENSEIRB, UMR 5218 CNRS, 351 cours de la Liberation, 33405, Talence Cedex, France

    Francois Marc

Authors
  1. Olivier Heron
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  2. Clement Bertolini
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  3. Chiara Sandionigi
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  4. Nicolas Ventroux
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  5. Francois Marc
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Correspondence to Olivier Heron.

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Responsible Editor: D. Gizopoulos

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Heron, O., Bertolini, C., Sandionigi, C. et al. On the Simulation of HCI-Induced Variations of IC Timings at High Level. J Electron Test 29, 127–141 (2013). https://doi.org/10.1007/s10836-013-5368-x

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  • DOI: https://doi.org/10.1007/s10836-013-5368-x

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