Journal of Electronic Testing

, Volume 28, Issue 4, pp 523-534

First online:

Open Access This content is freely available online to anyone, anywhere at any time.

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

  • Mottaqiallah TaouilAffiliated withFaculty of EE, Mathematic and CS, Delft University of Technology Email author 
  • , Said HamdiouiAffiliated withFaculty of EE, Mathematic and CS, Delft University of Technology


Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.


3D stacked-IC Yield enhancement Memory redundancy 3D memory Wafer matching