High Speed On-Chip Signal Generation for Debug and Diagnosis
- First Online:
- Cite this article as:
- Tsai, TY., Aouini, S. & Roberts, G.W. J Electron Test (2012) 28: 625. doi:10.1007/s10836-012-5289-0
- 866 Downloads
This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma–delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for-test (DFT), or built-in self-test (BIST).
KeywordsAnalog testMixed-signal testDesign-for-testBuilt-in self-testPhase generationFrequency synthesisSigma-data encodingIntegrated circuitPhase-locked loop
Traditionally, information has been processed and encoded in the voltage/amplitude domain; however, more recently the encoding of information in time has gained considerable popularity  and . Time mode signal processing involves encoding the information in the form of time difference variables using phase modulation. A digital-to-time converter (DTC) can be seen as any device used to map a digital value to a time-based signal, similar to a digital-to-analog converter (DAC) in the voltage/amplitude domain. Likewise a digital-to-frequency converter (DFC) converts a digital code to a corresponding instantaneous frequency. From a system perspective, such a conversion process should always be combined with a reconstruction filter to eliminate the images in the output spectrum. In , it has been shown that a phase-locked loop can be used as a reconstruction filter for DTCs.
The test implementation as presented is appropriate for testing analog circuitry. For testing of digital circuits, proper buffering and/or level shifting may be required. As the PLL in this implementation is used as a time domain filter, any PLL with the appropriate bandwidth may be used. PLLs have been demonstrated to be built in 90 nm and 45 nm technologies; as such, the technique should be fully compatible with them. As this technique uses a bitstream and a PLL, it is scalable with technology and a higher speed implementation would be realizable.
This paper is divided as follows: first, the phase and frequency encoding process using sigma–delta modulation is described in Section 2. In Section 3, MATLAB/Simulink simulations are used to validate the technique. In Section 4, the design of a prototype phase/frequency test signal generator incorporating a custom high-speed PLL built in CMOS 0.13 μm and running at 4 GHz, and custom PCB used to interface the PLL chip to the test equipment are described. The experimental results are then outlined in Section 5 and finally, conclusions are drawn and future potential avenues are discussed in Section 6.
2 Phase and Frequency Encoding Using Sigma–Delta Modulation
In this section, an overview of the phase encoding process using sigma–delta modulation and digital-to-time conversion techniques is presented and then extended to frequency encoding using digital-to-frequency conversion.
2.1 Phase Encoding
It can be noted here that Eqs. 1 and 3 are related. In fact, in Eq. 1 we can convert tref to the phase domain by multiplying it by ωs (ωs = 2π/tS), where tS is sampling period of the DTC as shown on Fig. 1 to give αϕ. Likewise tos of Eq. 1 can be converted to tos by the same relationship.
2.2 Frequency Encoding
Assuming the quantization noise carried over from the sigma–delta encoding process is removed by a filtering function realized by the PLL, one can also show, following the previous subsection arguments, that the SNR of the DFC process has the same SNR as established by the sigma–delta encoding process.
3 MATLAB Modelling and Simulation Results
3.1 System Simulation
4 Phase/Frequency Generator Implementation
The phase/frequency generator consists of a cyclic memory element, containing a phase or frequency encoded sigma–delta bitstream, and a custom phase-locked loop whose bandwidth corresponds to that of the software-based sigma–delta modulator. This system is shown in Fig. 11. The details of both the cyclic memory and the design of the custom PLL are described, as well as the design of a PCB that allows the PLL to interface with test equipment.
4.1 Cyclic Memory
The phase/frequency generator requires a cyclic memory element in order to present an uninterrupted phase or frequency encoded bitstream to the PLL. This is accomplished by using an external pattern generator, further described in the Experimental Results section. Any programmable memory element can be used for this purpose (e.g., a FPGA).
4.2 Custom PLL Design
In order to test frequency and phase synthesis at high speeds, a custom PLL had to be designed and built. A top-down design methodology was employed to impose a desired phase transfer function, as described in . The IBM cmrf8sf 130 nm process was chosen as the technology for fabrication.
4.2.1 Transistor-Level Design
Initially, the loop filter was planned to be implemented on chip. A passive, LC-ladder based approach was first considered; however, restrictions on zero placement made it unsuitable for the transfer function of the filter. Gm-C filters were evaluated next as an option. For a filter of with a bandwidth of around 1 MHz, the gm values required from each cell would be on the order of 1 × 10 − 6 to 1 × 10 − 7. This is difficult to achieve in a gm-cell, as the bias currents would have to be correspondingly small as well. For similar reasons, an active RC implementation would be less than ideal, due to the large RC constants (and capacitors) that would be required. Switched-capacitor filters were considered, but with time restrictions imposed by the tape-out deadline, it was decided to move the loop filter off-chip.
4.3 PCB Considerations
In order to interface between the PLL to off-board equipment and instrumentation, a printed-circuit board (PCB) must be designed and fabricated.
Chip-Bonded PCB The PCB is intended to host the PLL die as well as the loop filter. It incorporates design features which aid in high-speed operation, such as microstrips, 50 impedance SMA connectors, and Rogers 4003 material (for greater dielectric uniformity).
The width of the line was found to be 17 mils, which gives a Zo of approximately 51.9 Ω. These microstrips were selected for impedance control for manufacturing, so a test coupon was created to measure their impedance. The test report states an impedance of 45.97 Ω on average, which is close to the desired value.
Component Selection Due to concerns about the charge pump drive capability, efforts were made to minimize the parasitic capacitance offboard. To this end, package style of 0402 components were used, as well as the LFCSP package for the AD8045 opamp. Snap-on terminal blocks are used for the power connections to allow for quick connection and disconnection to the power supply, allowing for quick changes to be made to the PCB. Nylon standoffs were used on the corners of the PCB to reduce the chances of accidental shorts due to a messy workbench.
5 Experimental Results
Using the PCB with bonded PLL die, the functionality and performance of the phase and frequency signal generation system is explored. Some of these results were partially presented in ; the test results are presented in their entirety here.
5.1 Test Setup
5.2 Clock Input
Prior to testing frequency and phase signal generation, some basic PLL functionality has to be verified. For this purpose, the aforementioned pattern generator and an Agilent 33250A function generator was used to drive the PLL input with a clock. The function generator was used to sweep the input to check the lock and capture range of the PLL. It was found with the VCO powered from 1.2 V, the capture range is around 59 MHz to 69 MHz (3.776–4.416 GHz output). With the VCO being powered from 1.3 V, the capture range is 72.5 MHz to 80 MHz (4.640 GHz–5.120 GHz output). The lock range is found to be similar. This operational region is stable across several samples tested (three dies/boards). After this region, increasing the input frequency results in output from the VCO that is distorted and non-sinusoidal. However, it can observed that the PLL is tracking the input frequency on the spectrum analyzer as the output frequency is changing. Increasing the PLL input frequency past this region usually results in a narrow band of operation that locks with a sinusoidal output; however, the location of the region varies with the die tested (between 5 and 6 GHz roughly). Further tests are performed in the 59–69 MHz input range, as this is the widest region of operation and is constant across different dies.
Clock measurement results
Lock/Capture range @ 1.2 V
59 MHz–69 MHz
Lock/Capture range @ 1.3 V
72.5 MHz–80 MHz
Phase noise, 67 MHz input
−70 dBc/Hz @ 1 MHz
Cycle-to-cycle jitter, 67 MHz input
5.3 Frequency Signal Generation
DFC carrier frequency (MHz)
PLL output frequency (GHz)
5.4 Phase Signal Generation
Phase output results
Measured offset (ps)
Adjusted offset (ps)
6 Future Research
A phase/frequency signal generator for high-frequency applications amenable to digital testing methodologies without additional test pins was presented. The generator was implemented by means of a cyclic memory element and a custom integrated PLL. Although phase noise performance is much less than a fractional-N synthesizer, it is nevertheless useful for various debug and diagnosis situations that a design or test engineer may be in. In future research, a complete on-chip implementation with integrated loop filter will be investigated.