Journal of Electroceramics

, Volume 13, Issue 1, pp 417–422

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

  • Rao R. Tummala
  • P. Markondeya Raj
  • Steve Atmur
  • Shubhra Bansal
  • Sounak Banerji
  • Fuhan Liu
  • Swapan Bhattacharya
  • Venky Sundaram
  • Ken-ichi Shinotani
  • George White
Article

DOI: 10.1007/s10832-004-5135-6

Cite this article as:
Tummala, R.R., Raj, P.M., Atmur, S. et al. J Electroceram (2004) 13: 417. doi:10.1007/s10832-004-5135-6
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Abstract

The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform.

The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 μm lines/space widths and 40 μm pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive.

This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.

Keywords

FR4 electronic packaging high density packaging System-On-Package Printed Wiring Board SiC flip chip reliability high density wiring 

Copyright information

© Kluwer Academic Publishers 2004

Authors and Affiliations

  • Rao R. Tummala
    • 1
  • P. Markondeya Raj
    • 1
  • Steve Atmur
    • 2
  • Shubhra Bansal
    • 1
  • Sounak Banerji
    • 1
  • Fuhan Liu
    • 1
  • Swapan Bhattacharya
    • 1
  • Venky Sundaram
    • 1
  • Ken-ichi Shinotani
    • 3
  • George White
    • 1
  1. 1.Packaging Research CenterGeorgia Institute of TechnologyAtlantaUSA
  2. 2.Steve AtmurStarfire Systems Inc.MaltaUSA
  3. 3.Matsushita Electric WorksR&D Lab. Inc.Mountain ViewUSA

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