Journal of Computational Electronics

, Volume 11, Issue 1, pp 118–128

Monte Carlo study of self-heating in nanoscale devices

Authors

    • Department of Biomedical Engineering and Computational ScienceAalto University
  • Robert W. Kelsall
    • Institute of Microwaves and Photonics, School of Electronic and Electrical EngineeringThe University of Leeds
  • Neil J. Pilgrim
    • Institute of Microwaves and Photonics, School of Electronic and Electrical EngineeringThe University of Leeds
  • Jean-Luc Thobel
    • IEMN UMR-CNRS 8520Université Lille 1
  • François Dessenne
    • IEMN UMR-CNRS 8520Université Lille 1
Article

DOI: 10.1007/s10825-012-0395-x

Cite this article as:
Sadi, T., Kelsall, R.W., Pilgrim, N.J. et al. J Comput Electron (2012) 11: 118. doi:10.1007/s10825-012-0395-x
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Abstract

Progress in device miniaturization combined with the increase in integrated circuit packing density, as described by Moore’s law, have been accompanied by an exponential increase in on-chip heat generation. In this context, there is an increasing demand for reliable electrothermal modeling techniques that accurately account for self-heating and allow a better understanding of thermal transport at the nanoscale. This paper presents a theoretical demonstration of the electrothermal phenomena in a variety of nanodevices, ranging from conventional Si- and III-V-based field-effect transistors (FETs) to nanowire devices. Simulation work relies on a very well-established Monte Carlo simulator considering self-heating using phonon statistics. The electrothermal simulator self-consistently couples a three-dimensional (3D) electronic trajectory simulation with the solution of the heat diffusion equation. The Monte Carlo technique is very suitable for the simulation of electronic transport in nanoscale semiconductor devices, as it is free from low-field near-equilibrium approximations. In addition, the method is well-suited for electrothermal modeling, since it allows a detailed microscopic description of electron-phonon scattering which provides an inherent and direct prediction of the spatial distribution of heat generation. The paper is divided into three parts. The first part includes a description of the computational approach to simulate electrothermal transport in FETs. The advantages of using the simulation method are demonstrated by presenting full results from the simulation of an InGaAs-channel high-electron mobility transistor (HEMT). The second part concerns electrothermal transport in conventional field-effect devices such as Si and III-V HEMTs. An investigation of self-heating effects in high-power devices, such as AlGaN/GaN HEMTs, and relevant Si-based FETs, e.g. Si/SiGe HEMTs, is presented. This part demonstrates how the analysis of self-heating effects may help us in understanding the electronic and thermal properties of nanoscale FETs. The third part of the paper consists of studying the electrothermal behavior of advanced structures. In this case, charge transport and self-heating effects are investigated in metal-insulator-semiconductor FETs (MISFETs) with a single InAs nanowire channel. Despite low heat dissipation, simulations predict significant local temperatures, due to the high current density levels and the poor thermal management in these nanowire structures.

Keywords

Self-heatingElectron transportThermal transportElectrothermal modelingMonte CarloNanoscale semiconductor devicesSi/III-V heterostructure FETsNanowire MISFETs

1 Introduction

The semiconductor industry has witnessed a considerable growth in the last few decades, relying essentially on device miniaturization to increase the packing density and hence the functionality of integrated circuits (ICs). These improvements have roughly followed a trend described by Moore’s law, suggesting that the number of transistors on an IC for minimum component cost doubles every two years [1]. However, this progress has also been followed by an increase in the heat generation following a similar trend. As indicated in the survey presented in [2] regarding the trend of on-chip heat generation for different semiconductor corporations over the past 20 years, continuation of such trend towards the miniaturization of ICs will result in heat generation and temperatures reaching levels which will not allow for normal operation. This suggests that thermal transport has a critical role in future nanoscale devices, and therefore must be considered in the simulation of these devices, to obtain more reliable characteristics and allow the investigation of new designs for optimum thermal management. This work is a full theoretical study of a wide range of semiconductor devices using a self-consistent electrothermal Monte Carlo (MC) simulation method. Electron transport is analyzed in nanoscale field-effect transistors (FETs) based on silicon and compound semiconductors, including III-As and III-N materials, with special attention given to self-heating effects in these devices.

1.1 Self-heating effects in semiconductor devices

Device self-heating is becoming one of the main technological roadblocks of the predicted device miniaturization trends. In fact, power densities are expected to reach levels that will not permit normal operation of ICs, necessitating the development of accurate electrothermal simulators to investigate new designs minimizing self-heating effects. As illustrated in [2], the current on-chip heat generation levels are of the order of 100 W/cm2. The sustainment of this miniaturization trend in the next 10 to 20 years will lead to unrealistic power density levels (approximately 1000 W/cm2) and temperatures, making the operation of electronic devices impossible without significant improvements in cooling technology or fundamental changes in device designs. Therefore, thermal effects are an important consideration in the design of next-generation devices.

The simulation of carrier transport in nanoscale FETs requires an accurate coupling between electronic and lattice dynamics to account for self-heating effects. Heat generation in small devices is a direct consequence of the importance of nonequilibrium carrier transport in the active region of these structures. In areas where the electric field is high, the accelerated carriers collide with the lattice resulting in the emission of a large number of phonons which contribute to heat transport in the devices. Only acoustic phonons, generated from acoustic electron-phonon scattering or the decay of optical phonons, contribute directly to heat transfer [3]. Optical phonons are characterized by a very small group velocity and therefore their contribution to heat conduction is usually neglected. The static nature of optical phonons results in their accumulation in large numbers in high-field areas, giving rise to nonequilibrium optical phonon distribution functions. These nonequilibrium phonon distributions, associated with the hot-phonon effect [4], influence directly electron transport by modifying electron-phonon scattering rates.

An important challenge facing device designers, in addition to high power density levels, is the efficiency of the heat removal system in next-generation devices. Future heterostructure FETs incorporate layers of low thermal conductivity, such as III-V related alloys [5] in III-V high-electron mobility transistors (HEMTs) and SiGe alloys [6] in strained Si/SiGe HEMTs. Other attractive devices based on semiconductor-on-insulator (SOI) technologies also face thermal management problems, as they incorporate low thermal conductivity insulator layers such as SiO2. The use of low thermal conductivity substrates, such as sapphire in high-power GaN-based HEMTs, also degrades the device performance. More importantly, confined-geometry structures, such as HEMTs, FINFETs and nanowire devices, include structures thinner than the phonon mean free path, which are characterized by a thermal conductivity lower than that of the related bulk materials, due to phonon confinement and boundary scattering [3]. In particular, structures such as nanowires may be characterized by high current densities (and high power densities) giving rise to high temperatures, as illustrated in Sect. 4.

1.2 Electrothermal device modeling

There exist several methods for the modeling of electrothermal effects in semiconductor devices, ranging from equivalent circuit to more complex physical models. Initial electrothermal simulators based on drift-diffusion models involved the coupling of carrier transport with the solution of a set of differential equations, including Poisson’s equation, the current continuity equation and the heat diffusion equation (HDE) [710]. In these models, the power density is given by the dot product of the current density (J) and the electric field (E), with the assumption that Joule heating is dominant in the simulated devices. Due to the limitations imposed by the use of the drift-diffusion method, mainly the failure to reproduce nonequilibrium transport effects, interest then shifted to the inclusion of thermal effects in improved approaches to carrier transport simulation, such as the hydrodynamic method [11].

The correct assessment of the effect of device self-heating involves the coupling of accurate nonequilibrium charge transport simulation methods such as Monte Carlo, which is free from the approximations made in the drift-diffusion or hydrodynamic models, with lattice dynamics. Prior to this work, the Monte Carlo method has been used by several authors to study heat generation in semiconductor devices (e.g. [12]) without the inclusion of electrothermal self-consistency. The first attempt to studying self-heating effects in FETs using an electrothermal Monte Carlo simulator was made by Yoder and Fichtner [13]. The work presented in [13] was limited to the study of the influence of lattice temperature on the oxide lifetimes in metal-oxide-semiconductor field-effect transistors (MOSFETs), and included only a brief analysis of the effect of self-heating on charge transport in these devices. Another electrothermal Monte Carlo simulation model has been introduced by Kamoua [14] to simulate high-frequency transferred electron device (TED) oscillators. Although the work published in [14] did not focus on the thermal analysis of TED oscillators, it presented an interesting result regarding temperature rise in such structures. In recent years, other interesting work on electrothermal Monte Carlo modeling has also appeared [15, 16]. To the author’s knowledge, the electrothermal Monte Carlo FET simulator used in this work is the first of its kind, in terms of model accuracy and its applicability to a wide range of unipolar (n-type) heterostructures and nanowires.

2 The electrothermal Monte Carlo simulator

The Monte Carlo method accurately describes electron transport in FETs, as it accounts for different effects present in semiconductors, such as electron scattering processes and electronic bandstructures, at a very fundamental level [17]. Monte Carlo simulations are performed self-consistently, studying the trajectory of tens of thousands of weighted particles moving in an electric field distribution determined by solving Poisson’s equation. Thermal self-consistency is included by iteratively coupling the Monte Carlo electronic trajectory simulation with the solution of the HDE using phononic statistics. The flowchart shown in Fig. 1 highlights the main steps used in the electrothermal Monte Carlo model. The initial Monte Carlo iteration is run at an ambient temperature distribution of 300 K for 20–30 ps, which is enough for electron transport to reach a steady-state. As the steady-state is approached, electronic parameters are sampled for another 20–30 ps to generate the results from this iteration, including the power density distribution. The average thermal power density (net phonon power emission density) distribution is determined in the simulated region of the device using the net phonon emission approach [12], in which the number of phonon emission and absorption events are counted over the iteration period. This distribution is then fed to the HDE solver to update the spatially-varying temperature distribution in the simulated region. The Monte Carlo algorithm is then re-run with the new updated temperature distribution. The simulations are performed until the device terminal currents converge to their thermally self-consistent values. The number of electrothermal iterations needed for the terminal currents to converge to their electrothermal values, from isothermal conditions (at 300 K), depends on many parameters, such as the biasing condition, and is generally less than five.
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Fig. 1

The electrothermal Monte Carlo simulation procedure

Alternative approaches to simulating devices, including analytical models or numerical drift-diffusion or hydrodynamic simulations, usually account for self-heating effects by using temperature dependent steady-state electron drift velocity versus electric field (vE) curves [18]. This approach cannot be justified in areas where electron transport is at nonequilibrium, for example in the region below the gate of a HEMT where electrons are accelerated under the presence of high electric fields. Moreover, temperature dependent steady-state vE curves are generated assuming a balance of phonon absorption and emission events, a condition not satisfied in nonequilibrium areas where a significant amount of heat is generated. In terms of electrothermal modeling of the nanodevices considered in this work, most of the heat is generated in areas characterized by nonequilibrium transport, and therefore an accurate model to determine heat generation in such areas is necessary to obtain reliable device characteristics. Since the Monte Carlo method allows for accurate modeling of hot-electron transport, an accurate heat generation distribution is extracted from phonon scattering events, while other near-equilibrium methods rely on using simpler and less accurate heat generation calculation methods, such as the J⋅E model or the ‘I V’ model (where a uniform heat generation distribution is assumed in the active region of the simulated device with the total power given by the product of the device current (I) and the drain voltage (V)).

Simple analytical approaches to calculating the lattice temperature for use in numerical simulations have been developed and employed by several authors (see for example [19]). The most accurate approach to accounting for device self-heating requires the self-consistent simulation of phonon transport and phonon interactions, where only acoustic phonons contribute directly to heat transport. This approach involves the solution of the phonon Boltzmann transport equation, either by using numerical solvers or performing Monte Carlo calculations which require the study of the movements of a very large number of phonons in the semiconductor die for at least the duration of thermal transients. These solution methods cannot be readily implemented, as they are extremely time-consuming and computationally-complex. The electrothermal coupling scheme employed here is more convenient for use in the simulations than the schemes discussed above, as it provides reliable results at a reasonable computational cost.

2.1 Simulation details

The simulation method is an iterative procedure using phonon statistics to self-consistently couple a (2D/3D) Monte Carlo trajectory simulation method with the solution of the (2D/3D) time-independent heat diffusion equation (HDE). The electrothermal coupling equations, including the HDE and the related heat generation term, are described in [20]. Each electrothermal Monte Carlo iteration includes a transient period (up to 30 ps) to allow the electronic characteristics to reach steady state, and an equilibrium period (up to 30 ps) where electronic (e.g. drain current, ensemble electron velocity and energy distributions) and thermal statistics (e.g. heat generation distribution) are taken. During a Monte Carlo simulation, Poisson’s equation is solved every 0.5 fs. An important issue arising from the coupling of an electronic transport simulation to any thermal model is the significant difference in the characteristic time scales of electronic and thermal transport. Electronic transients in semiconductor systems are of the order of picoseconds, whereas thermal transients may be of the order of nanoseconds, microseconds, or even longer. While performing Monte Carlo computations for the duration of thermal transients would not be feasible, it is also not necessary when studying static DC electrothermal characteristics, as is the case in this work. Consequently, the method used here extracts steady-state electrothermal device characteristics only, by solving the time-independent HDE once at the end of each Monte Carlo iteration.

Another important issue concerning electrothermal coupling is the great difference in the characteristic space-scales of electronic and thermal transport. Electron transport is only studied in the device active region whose volume is of the order of few cubic microns, since transport outside this region is at equilibrium (where the electronic system is in equilibrium with the lattice) and the amount of heat generated is negligible, while heat diffuses over the whole semiconductor die whose volume is of the order of thousands of cubic microns. This problem is solved by assuming that heat is only generated in the electronically simulated region. The HDE is numerically solved to determine the temperature distribution in this region while considering the thermal boundary conditions at the surfaces of the semiconductor die. The thermal domain is simulated as a cuboidal die with adiabatic boundary conditions imposed on the top and side surfaces and an ideal heat-sink kept at a fixed temperature (300 K) at the base. By considering the boundary conditions applied in this work, it can be demonstrated that a reduction in the die length results in an increase in the device temperature while a reduction in the die depth results in a decrease in the temperature (see for example [21]). The thermal model does not account for temperature changes beyond the semiconductor die. Radiation losses are neglected, as their contribution at the small die surface areas is insignificant [22]. Convective losses can also be ignored for these systems [22], although both effects can be included if necessary [23]. Figure 2 is an illustration of the space- and time-scale differences between the electronic and thermal domains of simulation.
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Fig. 2

Differences in the space- and time-scale differences between the electronic and thermal domains of simulation. L, W and D represent the die length, width and depth, respectively

Simulation can be performed in two or three dimensions by employing either finite-difference (FD) or finite-element (FE) discretization methods. The chosen simulator complexity depends on the nature of the studied structures. Initial work on conventional FET structures relied mostly on the 2D FD scheme. In such simple geometries, employing 2D solvers based on analytical models or finite-difference meshing is sufficient for a reliable study of the coupled effect of electron transport and heat diffusion. The 2D FD version of the electrothermal Monte Carlo method has been successfully employed to study transport in heterostructure devices based on several material systems, including Si [24, 25], III-As [20] and III-N [2628] compounds. Later work on the modeling of advanced structures such as nanowires and nanojunctions involved the use of the 3D FE schemes [2935]; for this purpose, substantial efforts have been invested to carefully integrate into our simulator a finite-element package (NETGEN/NGSOLVE [36]) to solve for both Poisson’s and the heat diffusion equations. This package provides efficient device meshing and a reliable solution of these equations, irrespective of the level of complexity of the simulated device geometry. For the nanowire-based FET structures simulated here, 3D modeling using finite-element meshing is essential for the correct inclusion of the shape of the metallic contacts as well as the nanowire diameter and gate-oxide thickness in the simulations.

Since the main aim of this work is to demonstrate electrothermal effects in nanodevices, we use analytical ellipsoidal/spherical non-parabolic models to describe the bandstructure of the Si and III-V materials considered here. Depending on the material system, the simulator considers the effect of all the important scattering mechanisms, including intravalley acoustic and optical phonon scattering, intervalley phonon scattering, ionized impurity scattering, alloy disorder, electron-electron interactions and electron degeneracy. The effect of non-equilibrium phonon distributions (hot-phonon effect) [37], a phenomenon directly associated with thermal effects, is also included in the simulation model. While this phenomenon plays a significant role in the absence of self-heating in III-V structures, its impact may not be as important as temperature rise at electrothermal conditions and is negligible in Si-based systems. Unless otherwise stated, this effect is not included and equilibrium phonon occupation numbers, determined from the Bose-Einstein distribution, are used in the phonon scattering rate formulas. In spite of the relatively large depth of the quantum wells (10–15 nm) and nanowire diameter (50 nm) of the devices studied here, the presence of quantization effects may play a role in determining some aspects of the device characteristics, mainly the free-carrier distribution in the (two-dimensional yz) plane perpendicular to the direction of transport (x-direction). Nonetheless, these effects are not expected to affect significantly the quantitative and qualitative conclusions made regarding electrothermal effects. Quantization effects may be considered by the coupling of the solutions of Poisson’s and Schrödinger equations. However, the application of this procedure results in a significant increase in simulation time, and hence such effects are not accounted for in this work.

2.2 Advantages

This section aims to illustrate the advantages of our simulator by studying a 200 nm-gate-length InGaAs/AlGaAs HEMT, as shown in Fig. 3. One of the main advantages of using the Monte Carlo method for electrothermal modeling is the fact that it provides a very accurate determination of heat generation distribution in a device, obtained directly from the individual electron-phonon interactions. Figure 4 shows the power density distribution in the electronically simulated region obtained from both the net phonon emission and the J⋅E methods, at a given bias. Clearly, the distribution obtained using the J⋅E method is more localized than that obtained using the net phonon emission method, with strange effects observed along the channel. The discrepancies observed are due to the fact that the J⋅E product does not reflect the nonequilibrium nature of electron transport in FETs [38]. The localized nature of this term leads to inaccurate prediction of heat generation in some parts of the device; the J⋅E approach assumes that energy transfer occurs instantaneously and is co-located with electron heating.
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Fig. 3

Schematic structure of the electronically simulated region of the HEMT

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Fig. 4

Power density distribution obtained using (left) the net phonon emission approach, and (right) the J⋅E approach, at gate-to-source and drain-to-source biases of 0.0 V and 2.0 V, respectively

The use of the net phonon emission method has the benefit of allowing the study of the contribution of the individual phonon populations to heat generation in the simulated devices. Figure 5 shows the total heat generated from the different phonon populations. In the simulated InGaAs/AlGaAs HEMT, phonons contributing to thermal transport include, in addition to intravalley acoustic phonons, Γ-point optical phonons mediating intravalley transitions and X-point and L-point optical phonons mediating intervalley transitions. Γ phonons are the largest contributors to heat generation closely followed by X phonons. Clearly, the contribution of intravalley acoustic phonons to the total net phonon emission is small. In general, the calculated total net phonon emission power is slightly smaller than the total macroscopic power (obtained from the product of the drain current and the drain-to-source bias) for several reasons, mainly the neglect of all the heat generated outside the electronically simulated region by electrons with over-ambient energies (>1.5KBT) escaping from the simulated region.
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Fig. 5

The total net phonon emission by phonon populations, at a gate-to-source bias of 0.0 V

Another important advantage of using the Monte Carlo method is that it allows an accurate study of the effect of self-heating on the microscopic properties of electron transport, which could be used to predict the influence of this effect on the macroscopic electronic and thermal properties of the devices. Figure 6 shows the profiles of the mean value of the x component of the electron velocity along the channel, at a given bias, for both isothermal (at 300 K) and electrothermal simulations. A reduction in the velocity along the channel is observed when including electrothermal self-consistency; temperature rise in the channel increases the number of electron-lattice collisions, effectively reducing the average momentum and hence velocity in the horizontal x direction. Since most of the current flows through the channel, the reduction in velocity may be related directly to the reduction in the device current due to the inclusion of self-heating effects. Figure 6 also shows the velocity profiles obtained from an isothermal simulation in which the lattice temperature was set to the peak temperature obtained from an electrothermal simulation under the same biasing condition. Clearly, this approximate approach to account for self-heating leads to an underestimation of the velocity (and the drain current) in most parts of the channel. This particular observation demonstrates the need for accurate modeling of thermal effects in nanoscale devices for reliable results to be produced from device simulations.
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Fig. 6

Mean x component of the electron velocity along the channel, for isothermal and electrothermal simulations. The mean velocity along the channel for a uniform peak self-consistent temperature is also shown. The gate and the drain biases are 0.5 V and 3.0 V, respectively

3 Heterostructure FETs

In this section, the electrothermal performance of an InGaAs/AlGaAs HEMT (shown in Fig. 3), an AlGaN/GaN HEMT [26] and a strained Si/SiGe HEMT [24], is simulated and compared. To make the comparison more meaningful, all the three devices are assumed to have a 0.2 μm gate length, a 100 μm die length, a 100 μm die width and a 100 μm die depth. The drain-source spacing is taken to be 0.8 μm and it is assumed that the gate-source and the gate-drain separations are the same. The GaN HEMT is grown on top of a SiC substrate with a 1 μm n-type GaN buffer layer under the channel. The layer structure of the devices is shown in Fig. 7
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Fig. 7

Schematic structure of the electronically simulated region of the AlGaN/GaN and the strained Si/SiGe HEMTs

A direct means of comparing the thermal management efficiency is to plot the variation of the peak temperature with the total macroscopic power dissipation in the three structures, at a given gate-to-source bias, as shown in Fig. 8. The derivative of these plotted trends (\(\frac{\partial T_{\mathit{max}}}{\partial P_{\mathit{mac}}}\)) can be used as an indicator of the efficiency of thermal management, with lower values implying better device thermal management. From Fig. 8, it can be concluded that the GaN HEMT gives the best thermal performance because of the high thermal conductivity of the buffer and substrate materials used. The SiGe HEMT provides the poorest thermal performance mainly due to the very low thermal conductivities of SiGe alloys (κ∼7 W m−1 K−1 for Si0.7Ge0.3 at 300 K) [6]. However, as demonstrated in [24], the thermal performance of this device may be significantly improved by using thinner SiGe buffer layers. The reduction in the thickness of the SiGe buffer layers may allow better thermal management in SiGe HEMTs, as compared to GaAs HEMTs, taking advantage of the high thermal conductivity of silicon substrates (κ∼150 W m−1 K−1 for silicon and κ∼55 W m−1 K−1 for GaAs at 300 K).
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Fig. 8

Variation of the peak temperature with the total macroscopic power dissipation for the SiGe HEMT, the GaAs HEMT and the GaN HEMT, for a gate length of 0.2 μm. The data points are obtained at a gate bias of 0.4 V and for a selected number of drain biases within the corresponding drain biasing range of each device

Figure 9 shows the variation of the current reduction upon the inclusion of thermal self-consistency with the maximum reduction in the mean x component of electron velocity in the channel, for the three simulated devices. As expected, an approximate linear relationship is observed between the two parameters for all the three devices. Since, by current continuity, the slope of each curve (the ratio of the reduction in current to the reduction in velocity) is directly proportional to the 2DEG concentration, this parameter reflects the extent of 2DEG confinement in each device. As expected, the highest slope value is observed in GaN HEMTs because of the presence of polarization effects in these structures which create a very high 2DEG density. The second highest slope is observed in the GaAs HEMT due to the better 2DEG confinement at an In0.15Ga0.85As/Al0.28Ga0.72As interface, as compared to a strained Si/Si0.7Ge0.3 interface. This section provides a demonstration that devices with higher current handling capabilities do not necessarily give higher self-heating extent as long as an efficient heat removal system is used (involving for example high-thermal conductivity buffer and substrate layers such GaN and SiC).
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Fig. 9

Variation of the electrothermal reduction in the drain current with the electrothermal reduction in the peak x velocity in the channel for the SiGe HEMT, the GaAs HEMT and the GaN HEMT, for a gate length of 0.2 μm. The data points are obtained at a gate-to-source bias of 0.4 V and for a selected number of drain-to-source biases within the corresponding drain-to-source biasing range of each device

4 Nanowire FETs

In this work, we employ the three-dimensional finite-element version of the electrothermal Monte Carlo simulator to study metal-insulator field-effect transistors (MISFETs) based on a single InAs Nanowire. The model couples a 3D ensemble Monte Carlo simulation with the solution of the 3D heat diffusion equation, and is carefully calibrated with data from experimental work on these devices. Both Poisson’s and the heat diffusion equations are solved using a finite-element package (NETGEN [36]) integrated into our simulator, providing reliable device meshing and solution of these equations in complex geometry structures such as the studied nanowire devices. While nanowires are considered as one-dimensional structures, 3D simulations correctly accounting for the full device geometry, including the form of the metallic contacts as well the nanowire diameter, gate-oxide thickness and the buffer and substrate layers, are essential for an accurate analysis of electron transport and heat transfer in the nanostructures. The simulator is applied to investigate electron transport and demonstrate the importance of self-heating in such devices characterized by high current densities.

The results reported here are from the simulation of omega-shaped gate MISFETs [39] based on a 50 nm-diameter InAs nanowire. The great interest in these devices is justified, since they exhibit superior transport properties compared to InAs channel heterostructure FETs. Device characteristics of interest include excellent saturation behavior, and high breakdown voltage, current density and transconductance [39]. This work has the purpose of providing a better understanding of transport at the microscopic scale and demonstrating the importance of self-heating in these devices; the high current densities in the nanowire may be accompanied by high power densities in regions characterized by high electric fields, giving rise to considerable local temperatures inversely influencing transport. Furthermore, the low thermal conductivities of InAs nanowires and silicon nitride (SiNx) are physical factors that can also negatively affect thermal management in these structures.

The nanowire MISFET studied here (and in [39]) has a nanowire diameter (D) of 50 nm, a gate length (LG) of 1 μm and a gate-oxide thickness (TOX) of 30 nm. Figure 10 shows the full geometry used in the simulations. The structure is assumed to be built on a GaAs die with a fixed-temperature heat-sink (300 K) placed at its base surface. The die length, width and depth are all assumed to be 100 μm. Figure 11 illustrates the excellent agreement between the experimental data presented in [39], from the study of a 2 μm gate length MISFET, and the results we obtained from the simulation of this device. Figure 12 is a three-dimensional map showing the temperature distribution in the active region of the device, at high drain and gate biases. This figure illustrates how the peak temperature occurs near the gate-end of the drain. This result is expected since this region is characterized by high-electric fields accelerating electrons in the area. This observation is supported by Fig. 13 showing the variation of the mean electron energy and power density along the nanowire, for different oxide thickness values. Figure 13 demonstrates the creation of a hot-electron population in the region giving rise to significant heat generation. While the correlation between the energy and power density profiles can be easily observed, the peak in net phonon emission is ahead of the peak in electron energy, corresponding to the finite time needed for the highly-energetic electrons to start emitting phonons. It is observed that heat dissipation under the gate is more significant at thinner gate-oxide layers, where the effect of gate bias is more important. The temperature distributions also show a secondary peak located near the source-end of the gate whose value is directly dependent on gate bias. While a considerable thermal power is generated under the gate, the temperature is relatively low in this region since heat is easily evacuated through the gate contact (which is only separated from the nanowire by TOX (tens of nanometers)). Temperature in the ungated regions are relatively higher, despite the limited heat generation, because heat removal is more challenging in these regions where a very low thermal conductivity material SiNx surrounds the nanowire. Figures 14 and 15 show the peak and average temperatures in the nanowire, as a function of the macroscopic power dissipation. In general, the average temperature values are significantly lower than the peak temperature values. Such difference is a direct consequence of the strong localization of the power density distributions, where the elevated current densities in these devices give rise to elevated power densities, and hence high peak temperatures (up to 440 K), in regions characterized by high-electric fields. These high temperature levels may have serious effects on device long-term reliability and lifetime.
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Fig. 10

The simulated 3D geometry of the MISFET. The source-gate and the drain-gate (LS) separations are 0.5 μm

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Fig. 11

The measured and simulated IdVds characteristics of the 2 μm gate length MISFET studied in [39] at Vgs=1.9 V, and the measured and simulated IdVgs characteristics of this MISFET at Vds=3.0 V. Experimental data are from [39] and simulation data are from [29]

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Fig. 12

A 3D iso-temperature map at gate and drain biases of 3 V and 2.5 V respectively

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Fig. 13

Variation of the mean electron energy and power density along the nanowire, for different oxide thickness values, for relatively high gate and drain biases

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Fig. 14

Variation of the peak temperature with the total macroscopic power dissipation, for different oxide thickness values

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Fig. 15

Variation of the average temperature with the total macroscopic power dissipation, for different oxide thickness values

The global objective of this work is to demonstrate the ability of our simulation model to analyze the electrothermal behavior of advanced nanostructures. A systematic study of the nanowire FET basic output characteristics and the microscopic properties of electron transport were performed, demonstrating the dependence of the extent of self-heating on bias and geometrical parameters. More specifically, we demonstrated how such small devices characterized by a low power dissipation, may give significant temperature rise, which inversely affects their performance and reliability. Such conclusion is expected considering the combined effect of poor thermal management, attributed mainly to the low thermal conductivity of SiNx and the InAs nanowire, and the increased current density. This study is performed for InAs nanowire MISFETs, but the conclusions may be extended to similar nanostructures. The study of structures with similar complexity, such carbon-nanotube (CNT) FETs or graphene-based structure, may be considered using our simulator in the near future. In spite of the predicted excellent electrical and thermal properties of CNTs, studies suggest that electrothermal effects may play a significant role in CNT-based structures [40, 41]. These observations motivate research on electrothermal transport in CNTs and CNT-based devices, to better understand the electrothermal phenomenon in such structures. Further theoretical work is also urgently needed to simulate electrothermal transport in emerging graphene structures [42].

5 Conclusion

This paper concerns the simulation and analysis of self-heating effects and electron transport in a variety of nanoscale devices. The importance of self-heating has been highlighted in low-power devices, such as III-As and Si FETs, and in high-power III-N HEMTs. Electrothermal effects in advanced nanowire MISFETs were also demonstrated. It was shown that high internal temperatures will continue to be a serious problem in these nanostructures. Therefore, significant improvements in cooling technology and fundamental changes in device designs are required to guarantee normal operation for next-generation devices. To summarize, self-heating is one of the main considerations in the design of future semiconductor devices, necessitating the development of simulation models that accurately accounts for thermal self-consistency, as used in this work.

Acknowledgements

The first author would like to thank Prof. Frank Schwierz from the Technical University of Ilmenau for advice. The first author would also like to thank members of the Engineered Nanosystems team of Aalto University for valuable discussions.

Copyright information

© Springer Science+Business Media LLC 2012