Journal of Computational Electronics

, 8:441

An investigation of performance limits of conventional and tunneling graphene-based transistors

  • R. Grassi
  • A. Gnudi
  • E. Gnani
  • S. Reggiani
  • G. Baccarani
Article

DOI: 10.1007/s10825-009-0282-2

Cite this article as:
Grassi, R., Gnudi, A., Gnani, E. et al. J Comput Electron (2009) 8: 441. doi:10.1007/s10825-009-0282-2

Abstract

In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with non-ideal edges.

Keywords

Graphene nanoribbonsCarbon electronicsNanoelectronic devicesTunneling FET

Copyright information

© Springer Science+Business Media LLC 2009

Authors and Affiliations

  • R. Grassi
    • 1
  • A. Gnudi
    • 1
  • E. Gnani
    • 1
  • S. Reggiani
    • 1
  • G. Baccarani
    • 1
  1. 1.ARCES—Advanced Research Center for Electronics Systems, DEIS—Department of ElectronicsUniversity of BolognaBolognaItaly