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List Scheduling in Embedded Systems Under Memory Constraints

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Abstract

Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through adequate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20 % can be achieved. We also show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics. Lastly, we propose a methodology to assess the appropriateness of dynamic scheduling in this context.

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Notes

  1. The bottom level is also sometimes referred to as the upward rank.

  2. The orders of magnitude of the latency for local and external memories are respectively 1 cycle and 100 cyles.

  3. A token is the smallest unit of data that can be processed by a task. It is application specific; e.g. for an image-processing algorithm, it can be a line of pixels.

  4. Thus, from a processing viewpoint, pixel lines are independent.

  5. If a node can be pebbled more than once, then the problem is PSPACE-complete (and hence NP-Hard), but probably not in NP [10].

  6. As a reminder, the bigger its priority value, the earlier a task is scheduled.

  7. The sole purpose of this reference schedule is to serve as a basis to construct the self-timed schedule. Thus, the makespans resulting from it are not meaningful for our study and, as such, are not represented.

  8. To keep the model simple, interprediction is not considered.

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Authors and Affiliations

  1. Inria Bordeaux Sud-Ouest, Talence, France

    Paul-Antoine Arras, Emmanuel Jeannot & Samuel Thibault

  2. STMicroelectronics, Grenoble, France

    Paul-Antoine Arras, Didier Fuin & Arthur Stoutchinin

  3. University of Bordeaux, Bordeaux, France

    Paul-Antoine Arras & Samuel Thibault

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  1. Paul-Antoine Arras
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  2. Didier Fuin
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  3. Emmanuel Jeannot
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  4. Arthur Stoutchinin
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  5. Samuel Thibault
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Correspondence to Paul-Antoine Arras.

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Arras, PA., Fuin, D., Jeannot, E. et al. List Scheduling in Embedded Systems Under Memory Constraints. Int J Parallel Prog 43, 1103–1128 (2015). https://doi.org/10.1007/s10766-014-0338-1

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