The Coming Wave of Multithreaded Chip Multiprocessors
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The performance of microprocessors has increased exponentially for over 35 years. However, process technology challenges, chip power constraints, and difficulty in extracting instruction-level parallelism are conspiring to limit the performance of future individual processors. To address these limits, the computer industry has embraced chip multiprocessing (CMP), predominately in the form of multiple high-performance superscalar processors on the same die. We explore the trade-off between building CMPs from a few high-performance cores or building CMPs from a large number of lower-performance cores and argue that CMPs built from a larger number of lower-performance cores can provide better performance and performance/Watt on many commercial workloads. We examine two multi-threaded CMPs built using a large number of processor cores: Sun’s Niagara and Niagara 2 processors. We also explore the programming issues for CMPs with large number of threads. The programming model for these CMPs is similar to the widely used programming model for symmetric multiprocessors (SMPs), but the greatly reduced costs associated with communication of data through the on-chip shared secondary cache allows for more fine-grain parallelism to be effectively exploited by the CMP. Finally, we present performance comparisons between Sun’s Niagara and more conventional dual-core processors built from large superscalar processor cores. For several key server workloads, Niagara shows significant performance and even more significant performance/Watt advantages over the CMPs built from traditional superscalar processors.
- G. E. Moore, Cramming more Components onto Integrated Circuits, Electronics, 114–117, (1965).
- D. W. Wall, Limits of Instruction-Level Parallelism, WRL Research Report 93/6, Digital Western Research Laboratory, Palo Alto, CA (1993).
- J. D. Davis et. al., Maximizing CMT Throughput with Mediocre Cores in Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pp.51–62 (Sep. 2005).
- Standard Performance Evaluation Corporation, SPEC*, http://www.spec. org, Warrenton, VA.
- Transaction Processing Performance Council. TPC Benchmark C, Standard Specification Revision 3.6 (October 1999).
- Transaction Processing Performance Council, TPC-*, http://www.tpc.org, San Francisco, CA.
- XML Processing Performance in Java and .Net, http://java.sun.com/performance/reference/whitepapers/XML_Test-1_0.pdf
- S. Kunkel, R. Eickemeyer, M. Lip, T. Mullins, A Performance Methodology for Commercial Servers, IBM Journal of Research and Development 44(6): (2000).
- Kongetira P., Aingaran K. and Olukotun K. (2005). Niagara: A 32 way Multithreaded SPARC Processor. IEEE Micro 25(2): 21–29 CrossRef
- J. Laudon, Performance/Watt: The New Server Focus, in The Proceedings of the Workshop on Design, Architecture, and Simulation of Chip Multiprocessors, Barcelona, Spain (November 2005).
- Altschul S.F., Gish W., Miller W., Myers E.W. and Lipman D.J. (1990). Basic Local Alignment Search Tool: Basic Local Alignment Search Tool. Journal of Molecular Biology 215: 403–410
- The Coming Wave of Multithreaded Chip Multiprocessors
International Journal of Parallel Programming
Volume 35, Issue 3 , pp 299-330
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- Online ISSN
- Kluwer Academic Publishers-Plenum Publishers
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- Chip multiprocessing
- parallel programming
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