Formal Methods in System Design

, 35:190

Automating the addition of fault tolerance with discrete controller synthesis

Article

DOI: 10.1007/s10703-009-0084-y

Cite this article as:
Girault, A. & Rutten, É. Form Methods Syst Des (2009) 35: 190. doi:10.1007/s10703-009-0084-y

Abstract

Discrete controller synthesis (DCS) is a formal approach, based on the same state-space exploration algorithms as model-checking. Its interest lies in the ability to obtain automatically systems satisfying by construction formal properties specified a priori. In this paper, our aim is to demonstrate the feasibility of this approach for fault tolerance. We start with a fault intolerant program, modeled as the synchronous parallel composition of finite labeled transition systems; we specify formally a fault hypothesis; we state some fault tolerance requirements; and we use DCS to obtain automatically a program, having the same behavior as the initial fault intolerant one in the absence of faults, and satisfying the fault tolerance requirements under the fault hypothesis. Our original contribution resides in the demonstration that DCS can be elegantly used to design fault tolerant systems, with guarantees on key properties of the obtained system, such as the fault tolerance level, the satisfaction of quantitative constraints, and so on. We show with numerous examples taken from case studies that our method can address different kinds of failures (crash, value, or Byzantine) affecting different kinds of hardware components (processors, communication links, actuators, or sensors). Besides, we show that our method also offers an optimality criterion very useful to synthesize fault tolerant systems compliant to the constraints of embedded systems, like power consumption.

Keywords

Fault tolerant systemsDiscrete controller synthesisAutomatic fault tolerance

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.POP ART project-team and LIG laboratoryINRIA Grenoble Rhône-Alpes and Grenoble UniversitySaint-Ismier cedexFrance
  2. 2.SARDES project-team and LIG laboratoryINRIA Grenoble Rhône-Alpes and Grenoble UniversitySaint-Ismier cedexFrance