Wafer-scale fabrication of penetrating neural microelectrode arrays
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- Bhandari, R., Negi, S. & Solzbacher, F. Biomed Microdevices (2010) 12: 797. doi:10.1007/s10544-010-9434-1
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The success achieved with implantable neural interfaces has motivated the development of novel architectures of electrode arrays and the improvement of device performance. The Utah electrode array (UEA) is one example of such a device. The unique architecture of the UEA enables single-unit recording with high spatial and temporal resolution. Although the UEA has been commercialized and been used extensively in neuroscience and clinical research, the current processes used to fabricate UEA’s impose limitations in the tolerances of the electrode array geometry. Further, existing fabrication costs have led to the need to develop less costly but higher precision batch fabrication processes. This paper presents a wafer-scale fabrication method for the UEA that enables both lower costs and faster production. More importantly, the wafer-scale fabrication significantly improves the quality and tolerances of the electrode array and allow better controllability in the electrode geometry. A comparison between the geometrical and electrical characteristics of the wafer-scale and conventional array-scale processed UEA’s is presented.
KeywordsUtah electrode array (UEA)Neural interfaceMEMSHigh aspect ratioWafer-scale fabricationMicroelectrodes
In order to use an electrode array for stimulation and recording, uniformity and reproducibility of the electrode electrical and mechanical characteristics are of great importance. The geometrical architecture of the electrodes in the array defines their electrical and mechanical properties. This necessitates the need to develop a fabrication technology that is robust and that can produce uniformly shaped implantable microelectrodes with uniformly exposed tip sizes of the same order of magnitude as the neurons with which the electrode communicates (i.e., in the realm of micrometers).
Over the last two decades, microelectrodes have been produced as 2D and 3D arrays, mainly using silicon, glass, and metal microtechnologies (Kipke et al. 2003; Anderson et al. 1989; Drake et al. 1988; Bai et al. 2000; Mojarradi et al. 2003; Robinson 1968; Musallam et al. 2007; Schanne et al. 1968; Gagne & Plamondon 1987; Chowdhury 1969; Fofonoff et al. 2004; Jones et al. 1992; Campbell et al. 1991). Past attempts at manual assembling multiple sharpened metal (tungsten wire probes) and glass capillary probes into a linear array or a 2D matrix have been reported (Robinson 1968; Musallam et al. 2007; Schanne et al. 1968; Gagne & Plamondon 1987; Chowdhury 1969). However it is difficult to repeatedly control the geometry of such finished arrays. Furthermore the fabrication process to produce complex electrode arrays is labor intensive and is associated with low yields. Silicon based microelectrode arrays have previously been fabricated using surface micromachining (Michigan Electrode Array-MEA). The MEA is a 2D multichannel microelectrode array. Several of these 2D probes have been micro-assembled into 3D arrays (Kipke et al. 2003; Anderson et al. 1989; Drake et al. 1988; Bai et al. 2000). These probes are fabricated using fixed lithographic mask sets (typically a 5–10 mask process), which is also expensive and time consuming for small production volumes.
Conventionally, fabrication of the UEA’s has been carried out on a single array basis. Many of the manufacturing processes were unrefined. Furthermore, the manufacturing technique is time consuming, and yields less consistency in results than desired. With the greater experimental usage of the UEA, and the eventual need for production level requirements, the existing array-scale fabrication technique provides inadequate quality, repeatability, and throughput. In order to mitigate the challenges of the current array fabrication technology, the hypothesis for this work was to develop wafer-level processes for the UEA fabrication, however owing to the high aspect ratio (15:1) and non planar surface formed by the tips of the electrodes, the development of wafer-scale fabrication of the UEA poses many engineering challenges. In this paper, we present a wafer-scale manufacturing technique for fabricating the UEA, we identify problems and limitations associated with the array-scale fabrication and then report on some manufacturing innovations that will mitigate these problems. Wafer-scale fabrication of the UEA has several advantages including a simplified manufacturing process, higher yield, lower production costs, and reduced fabrication time. More importantly, the novel processing techniques not only allow higher throughput but also lead to more consistent electrode shape, more uniform and controlled tip exposure and uniform impedance of the electrodes. It is envisioned that these technological advancements in the UEA fabrication would in turn lead to better understanding of observed variations in physiological results.
2.1 Back-side dicing
To fill the diced kerfs with an insulating material a Corning 7,070 glass frit (325 mesh) is used, Fig. 2(c). This glass has a coefficient of thermal expansion close to that of silicon, and exhibits high volume resistivity (Jones et al. 1992). The glass powder is mixed to a slurry in methanol (1.2:1 by wt.) and applied to the grooved surface of the wafer, where it flows into the kerfs. The wafer is then dried in a oven at 60°C for 15 min. The wafer is then placed into a covered ceramic boat and loaded into a dental vacuum furnace (Ney Centrion Company, model # GQA0208104). A mechanical pump is connected to evacuate the furnace chamber, and the glass coated wafer is held under vacuum for 10–15 min to degas. The process is repeated 3-4 times until 3–5 layers have been coated. After this the wafer is sintered at 1,150°C. This allows the glass to melt and completely fill the saw kerfs.
The glassing procedure leaves an uneven layer of excess glass on top of the silicon wafer which is removed using a grinding process, Fig. 2(d). The grinding is achieved in three steps. In the first step the bulk glass is removed and the wafer is leveled in the dicing saw, using a resin bond, 0.6 mm thick blade. This step removes all the glass from the surface exposing the silicon surface with glass debris. In the second step, the wafer is lapped and polished using a customized stainless steel holder. The wafer is mounted on the holder using a semiconductor grade, wafer adhesive. The wafer is then manually lapped on 240, 320, and 600 grit size Silicon Carbide (SiC) paper for approximately 15 min for each grit. The SiC papers are mounted on a pottery wheel and wafer is manually lapped while the wheel is rotating. In the third and final step, the wafer is polished using a 9 μm and then 3 μm diamond suspensions on hard perforated cloth (Texmat AK8672) which is mounted on the pottery wheel. The wafer is finally polished in 1 um diamond suspension on medium nap polishing cloth (Microcloth AK 7222. This leaves a crosshatch pattern of insulating glass embedded on one side of the polished silicon wafer.
2.4 Back-side metallization
2.5 Front-side dicing
2.6 Wet etching
An important and early step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. The square columns fabricated by dicing are subsequently transformed into rounded and pointed electrodes through a wet etching process (mixture of HF (49%)-HNO3 (69%) in a ratio of 1:19) that rounds the column corners and sharpens the tip, Fig. 2(f). Etching of the UEA has two-steps consisting of (1) dynamic and (2) static etching (Campbell et al. 1991). Traditional etching processes are performed on a single array, and the etching conditions are not optimized. Furthermore the process is not only time and labor-intensive but also produces variable geometries of electrodes within an array. In order to achieve geometrical uniformity in electrodes, a wafer-scale etching method was developed and optimum etching conditions were investigated (Bhandari et al. 2010). A 100 mm diameter Teflon wafer holder was developed for wafer-scale wet etching of the 75 mm diameter diced wafers. Also a custom designed Teflon jig was built to continuously vent the gas evolved during static etching (Bhandari et al. 2010).
2.7 Tip metallization
To facilitate charge transfer from electrode to neural tissue the electrode tips are coated with a metal layer, Fig. 2(g) and the process is called “tip metallization.” Conventionally, Ti/Ir was sputter deposited and then electrochemically activated to form activated iridium oxide film (AIROF). A thin aluminum foil was used as a masking layer to protect the base of the device from sputtered metal. The aluminum foil is pierced by the electrodes to obtain the desired exposure. This is a single array process and cannot be implemented on wafer-scale (Campbell et al. 1991). Furthermore, aluminum foil masking process is manual and labor intensive.
A sputtered iridium oxide film (SIROF) process has been developed for tip metallization of the UEA. The unique properties of SIROF depend on the surface structure and the morphology of the films; hence, the process parameters have been optimized to procure efficacious and stable films. A detail description is given in previous publication (Negi et al. 2008).
An adhesion test was carried out to validate the affect of photoresist on the adhesion of SIROF on the electrode tips. To test the adhesion of SIROF on the electrode tips, PDMS sample was developed in accordance with ASTM (American Standard of Testing and Materials) protocol. The Young’s modulus of PDMS was measured by Instron 3360 and was found to be 220 kPa which is ten times more than the Young’s modulus of nerve, typically 34 kPa (Manduca et al. 2001). Five SIROF coated UEAs were inserted into the PDMS sample using a pneumatic impulse insertion technique that has been used successfully in cerebral cortex, and that has been described elsewhere (Rousche & Normann 1992). The impact inserter was positioned to apply a pressure of 200 kPa on the array to facilitate insertion direction during impact. Each array was inserted five times to a depth of 1.5 mm. The tips of each array were examined under SEM pre and post poking. No delamination of tip metal was seen under the SEM indicating good adhesion of SIFOF to silicon.
2.8 Parylene deposition
To improve the biocompatibility of the electrode array, Parylene-C is deposited in each individual UEA by using low-pressure chemical vapor deposition (LPCVD), Fig. 2(i) (Hsu et al. 2007). It is desired that each electrode array should be completely covered (except the back-side, which needs to be wire-bonded) with the encapsulating layer. This in-turn requires that each array should be singulated prior to the deposition. This prior singulation impedes wafer-scale fabrication of the UEA, particularly Parylene deposition and de-insulation of electrode tips. Furthermore in order to promote the adhesion of Parylene to the underneath substrate the UEA is subjected to wet silanization process prior to Parylene deposition (Hsu et al. 2007). Though both the Parylene deposition and silanization are batch processes they often lead to broken electrodes while handling.
A method was developed, in which the wafer, Fig. 2(h), was mounted on a carrier wafer, by using a wafer grip (Dynatex, lot# 09290701-01-JA). Then the arrays were singulated into 10 × 10 electrode arrays, using dicing saw. The blade height was adjusted to 2 mm (wafer thickness) so that arrays remain intact on the carrier wafer. The wafer was then coated with Parylene-C using chemical vapor deposition (CVD) process, a detailed description of which is given elsewhere (Hsu et al. 2007). Adhesion promoter, Silquest A-174® silane (GE Silicones Inc., WV, USA), was applied on the wafer prior to Parylene-C deposition. 3 μm thick Parylene-C films were deposited using a Paratech 3000 Labtop deposition system (Paratech Coating, Inc., CA, USA). Parylene-C dimer precursor was acquired from Cookson Electronics Equipment, USA. The dimer was vaporized at 130°C and subsequently pyrolized into reactive monomers at 670°C. The base pressure before Parylene dimer sublimation was less than 10 mTorr.
The Parylene-C encapsulation must be removed from the active electrode tips so that contact can be made to neural tissue, Fig 2(j). This is the most critical step as it defines the active area, called tip exposure. The geometrical surface area of the electrode tip has a significant impact on its electrical characteristics and selectivity. Uniformity in tip exposure is desired in order to predict the characteristics of an electrode array so that one can reliably interpret recorded signals during physiological experiments.
In conventional UEA manufacturing, tips are deinsulated using aluminum foil as a mask, by poking the electrodes through the foil to the desired exposure (Campbell et al. 1991). The exposed part of the electrodes is plasma etched while the aluminum foil protects rest of the device. This method of tip de-insulation has a few limitations. Repeatably and uniformly achieving tip exposure of 20 to 100 μm are very difficult. Also poking is a time consuming process: 15–20 min to poke one array. Poking is also operator dependent and hence is not a practical method for production. Handling arrays that have been wrapped in the aluminum foil is also a challenge as the tip exposure can change during handling, and the arrays can even be damaged.
Plasma etching conditions
Oxford Plasmalab 80plus
Comparison of nonuniformity in geometry and impedance of electrode arrays fabricated by the wafer-scale and the conventional array-scale method
Dynamic etching :column top
1.5% ± 0.5
9.68 ± 1.23
Static etching: (a) length
1.1 % ± 0.1
6.38% ± 4.6
(b) Shank width
1.36% ± 1.1
14% ± 5.15
4.08% ± 0.6
16.85% ± 3.42
20.76% ± 2.32
43.21% ± 12.11
Furthermore, the SIROF process along with photoresist based masking method allows wafer-scale tip metallization of UEA. The SIROF process requires no further conditioning and furthermore it reduces the cost of manufacturing and lead time. It must be noted that it takes approximately 2 h to activate one UEA with AIROF. There are 49 arrays in a 3-inch wafer, and hence it will take at least 98 h of parallel activation of arrays from one wafer. SIROF process would completely eliminate the activation process. It must be appreciated that using SIROF as an electrode material will not only increase the throughput, but most importantly, reduce any variation from the activation process, which will increase the reliability of the arrays. Additionally, SIROF will be of particular importance for the wireless recording/stimulating arrays, which by definition will not have wires that would allow activation via cyclic voltammeter.
This paper describes a wafer-scale method of fabricating high aspect ratio (15:1) penetrating microelectrode arrays with a reliable and reproducible process. The technique enables a low cost process and reduces lead time. Novel fabrication process such as, grinding, wet-etching, tip metallization, tip deinsulation have been incorporated in the UEA fabrication. These processes are not only performed on wafer-scale but also overcome the limitations of the existing technology and improve the quality and controllability in geometrical and electrical characteristics of the UEA. The wafer-scale technique and the individual process steps are platform technology and can be implemented to other configurations of the UEA such as the slant (Branner et al. 2001; Bhandari et al. 2009b) and the convoluted electrode arrays (Bhandari et al. 2008). The major advantage of this method compared to other techniques employed for fabricating high aspect ratio implantable devices is the simplicity of the method. The degree of control achieved in the dimensions and impedance of the electrode array would help in better understanding of observed variations in physiological results.
This work was supported in part by NIH/NINDS Contract HHSN265200423621C and by DARPA under Contract N66001-06-C-8005.