Analog Integrated Circuits and Signal Processing

, Volume 78, Issue 3, pp 557–571

Hardware-accelerated design space exploration framework for communication systems

Case studies in synthetic aperture radar and interference alignment processing
  • Markus Kock
  • Sebastian Hesselbarth
  • Martin Pfitzner
  • Holger Blume
Article

DOI: 10.1007/s10470-013-0127-6

Cite this article as:
Kock, M., Hesselbarth, S., Pfitzner, M. et al. Analog Integr Circ Sig Process (2014) 78: 557. doi:10.1007/s10470-013-0127-6

Abstract

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.

Keywords

Design space exploration (DSE)EmulationFixed-point arithmeticSynthetic aperture radar (SAR)Interference alignment (IA)

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Markus Kock
    • 1
  • Sebastian Hesselbarth
    • 1
  • Martin Pfitzner
    • 1
  • Holger Blume
    • 1
  1. 1.Institute of Microelectronic SystemsLeibniz Universität HannoverHannoverGermany