Analog Integrated Circuits and Signal Processing

, Volume 73, Issue 3, pp 931–944

Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

  • Gustavo Sanchez
  • Marcel Corrêa
  • Diego Noble
  • Marcelo Porto
  • Sergio Bampi
  • Luciano Agostini
Article

DOI: 10.1007/s10470-012-9944-2

Cite this article as:
Sanchez, G., Corrêa, M., Noble, D. et al. Analog Integr Circ Sig Process (2012) 73: 931. doi:10.1007/s10470-012-9944-2

Abstract

This article presents an architecture for the fractional motion estimation (FME) of the H.264/AVC video coding standard focusing in a good tradeoff between the hardware cost and the video quality. The support to FME guarantees a high quality in the motion estimation process. The applied algorithmic simplifications together with the multiplierless implementation and with a well balanced pipeline allow a low cost and a high throughput solution. The architecture was also designed to avoid redundant external memory accesses when computing the FME. The design was divided in two main modules: integer motion estimation (with diamond search algorithm) and fractional refinement (half-pixel and quarter-pixel interpolation and search). The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The architecture is able to reach 260 MHz when running in the target FPGA. In worst case scenario, this operation frequency allows a processing rate of 43 HD 1080p (1,920 × 1,080 pixels) frames per second, surpassing the requirements for real time processing. In comparison to related works, the developed architecture was able to achieve a good tradeoff among hardware costs, video quality and processing rate.

Keywords

Video codingH.264/AVC standardMotion estimationFPGA based design

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Gustavo Sanchez
    • 1
  • Marcel Corrêa
    • 1
  • Diego Noble
    • 1
  • Marcelo Porto
    • 1
  • Sergio Bampi
    • 2
  • Luciano Agostini
    • 1
  1. 1.Group of Architectures and Integrated CircuitsFederal University of PelotasPelotasBrazil
  2. 2.Informatics InstituteFederal University of Rio Grande do SulPorto AlegreBrazil