Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos
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This article presents an architecture for the fractional motion estimation (FME) of the H.264/AVC video coding standard focusing in a good tradeoff between the hardware cost and the video quality. The support to FME guarantees a high quality in the motion estimation process. The applied algorithmic simplifications together with the multiplierless implementation and with a well balanced pipeline allow a low cost and a high throughput solution. The architecture was also designed to avoid redundant external memory accesses when computing the FME. The design was divided in two main modules: integer motion estimation (with diamond search algorithm) and fractional refinement (half-pixel and quarter-pixel interpolation and search). The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The architecture is able to reach 260 MHz when running in the target FPGA. In worst case scenario, this operation frequency allows a processing rate of 43 HD 1080p (1,920 × 1,080 pixels) frames per second, surpassing the requirements for real time processing. In comparison to related works, the developed architecture was able to achieve a good tradeoff among hardware costs, video quality and processing rate.
- ITU-T e ISO/IEC JTC1. (1994). Generic coding of moving pictures and associated audio information—Part 2: video. ITU-T Rec. H.262 and ISO/IEC 13818–2 (MPEG-2).
- Vanne, J., Aho, E., Kuusilinna, K., & Hämäläinen, T. (2009). A configurable motion estimation architecture for block-matching algorithms. New York: IEEE Transactions on Circuits and Systems for Video Technology.
- Alencar, M. (2009). Digital television systems. Cambridge: Cambridge University Press.
- JCT. (2011). Working draft 3 of high-efficiency video coding. JCTVC-E603.
- Richardson, I. (2003). H.264 and MPEG-4 video compression–video coding for next-generation multimedia. Chichester: Wiley. CrossRef
- Bhaskaran, V., & Konstantinides, K. (1999). Image and video compression standards: algorithms and architectures (2nd ed.). Boston: Kluwer Academic Publishers.
- Tham, J., Ranganath, S., Ranganath, M., & Kassim, A. (1998). A novel unrestricted center-biased diamond search algorithm for block motion estimation. New York: IEEE Transactions on Circuits and Systems for Video Technology.
- Corrêa, M., Schoenknecht, M., Dornelles, R., & Agostini, L. (2011). A high-throughput hardware architecture for the H.264/AVC half-pixel motion estimation targeting high-definition videos. International Journal of Reconfigurable Computing, 2011. doi:10.1155/2011/254730.
- Choi, W., Jeon, B., & Jeong, J. (2003). Fast motion estimation with modified diamond search for variable motion block sizes. International Conference on Image Processing.
- Xiph.org: test media. Retrieved October, 2011, from http://media.xiph.org/video/derf/.
- JM 18. (2011). H.264/AVC JM reference software. http://iphome.hhi.de/suehring/tml.
- Porto, M., Silva, A., Almeida, S., Costa, E., & Bampi, S. (2010). Motion estimation architecture using efficient adder-compressors for HDTV video coding. Journal of Integrated Circuits and Systems, 5, 78–88.
- Kthiri, M., Loukil, H., Werda, I., Ben Atitallah, A., Samet, A., & Masmoudi, N. (2009). Hardware implementation of fast block matching algorithm in FGPA for H.264/AVC. International Multi-Conference on Systems, Signals & Devices.
- Tasdizen, O., et al. (2009). Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation. IEEE Transactions on Consumer Electronics, 55(3), 1645–1653. CrossRef
- Kao, C., et al. (2010). A high-performance three-engine architecture for H.264/AVC fractional motion estimation. IEEE Transactions on Very Large Scale Integration Systems, 18(4), 662–666.
- Lai, Y., et al. (2010). Hybrid parallel motion estimation architecture based on fast top-winners search algorithm. IEEE Transactions on Consumer Electronics, 56(3), 1837–1842. CrossRef
- Cetin, M., et al. (2011). An adaptive true motion estimation algorithm for frame rate conversion of high definition video and its hardware implementations. IEEE Transactions on Consumers Electronics 57(2).
- Altera Corporation. “Altera: The Programmable Solutions Company”. Available, from www.altera.com. Accessed Aug 2011.
- ModelSim. Available, from www.model.com. Accessed Aug 2011.
- Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos
Analog Integrated Circuits and Signal Processing
Volume 73, Issue 3 , pp 931-944
- Cover Date
- Print ISSN
- Online ISSN
- Springer US
- Additional Links
- Video coding
- H.264/AVC standard
- Motion estimation
- FPGA based design
- Industry Sectors
- Author Affiliations
- 1. Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil
- 2. Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, Brazil