Skip to main content
Log in

A new power-efficient CDMA-based transmitter for high-speed serial links

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

Conventional CDMA serial links suffer from the drawback that the number of transmitters is limited to only two in practical implementations due to the reduced voltage spacing between adjacent logic states of the transmitted data. In this letter, we propose a new CDMA serial link architect that allows an arbitrary number of transmitters to transmit data over the same channel while keeping the voltage spacing between adjacent logic states of the transmitted data to be the same as that of 4 pulse-amplitude-modulation serial link transmmitters. The effectiveness of the proposed architect is validated using the simulation results of a serial link with four transmitters designed in an IBM 130 nm 1.2 V CMOS technology.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

References

  1. Yang, C., & Lee, Y. (2008). A PWM and PAM signaling hybrid technology for serial-link transceivers. IEEE Transactions on Instrumentation and Measurement, 57(5), 1058–1070.

    Article  Google Scholar 

  2. Yuan, F. (2004). A fully differential 8-to-1 current-mode multiplexer for 10 Gbps serial links in 0.18-micron CMOS. IEE Electronics Letters, 40(13), 789–790.

    Article  Google Scholar 

  3. Yoshimura, R., Keat, T., Ogawa, T., Hatanaka, S., Matsuoka, T., & Taniguchi, K. (2000). DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs. In: Proceedings of the IEEE International Solid-State Circuit Conference (pp. 370–371).

  4. Chang, F., Poychowdhury, V., Zhang, L., Shin, H., & Qian, Y. (2001). RF/wireless interconnect for inter- and intra-chip communications. Proceedings of the IEEE, 89(4), 456–466.

    Article  Google Scholar 

  5. Kim, J., Xu, Z., & Cheng, F. (2003). A 2 Gb/s source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability. In: Proceedings of the IEEE Custom Integrated Circuits Conference (pp. 317–320).

  6. Cheng, F. (2005). CDMA/FDMA-interconnects for future ULSI communications. In: Proceedings of the IEEE/ACM International Conference Computer-Aided Design (pp. 975–978).

  7. Kim, J., Verbauwhede, I., & Chang, F. (2007). Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Transactions on VLSI, 15(8), 881–894.

    Article  Google Scholar 

  8. Xu, Z., Shin, H., Kim, J., Chang, F., & Chien, C. (2003). A 2.7 Gb/s CDMA -interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems. IEEE International Solid-State Circuit Conference, 1, 82–479.

    Article  Google Scholar 

  9. Brenna, G., Tschopp, D., Rogin, J., Kouchev, I., & Huang, Q. (2004). A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13 μm CMOS. IEEE Journal of Solid-State Circuits, 39(8), 1253–1262.

    Article  Google Scholar 

  10. Eloranta, P., Seppinen, P., Kallioinen, S., Saarela, T., & Parssinen, A. (2007). A multimode transmitter in 0.13 μm CMOS using direct-digital RF modulator. IEEE Journal of Solid-State Circuits, 42(12), 2774–2784.

    Article  Google Scholar 

  11. Papadopoulos, D., & Huang, Q. (2007). A linear uplink WCDMA modulator with-156 dBc/Hz downlink SNR. In: Proceedings of the IEEE International Solid-State Circuit Conference (pp. 338–339), Feb. 2007

  12. Jones, C., Tenbroek, B., Fowers, P., Beghein, C., Strange, J., Beffa, F., & Nalbantis, D. (2007). Direct-conversion WCDMA transmitter with −163 dBc/Hz noise at 190 MHz offset. In: Proceedings of the IEEE International Solid-State Circuit Conference (pp. 336–337), Feb. 2007.

  13. Sun, Z., Chi, B., Zhang, C., & Wang, Z. (2011). A 0.13 μm CMOS 1.5-to-2.15 GHz low power transmitter front-end for SDR applications. In: Proceedings of the IEEE International Symposium on Circuits Systems (pp. 2453–2456).

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Fei Yuan.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Al-Taee, A.R., Yuan, F. & Ye, A. A new power-efficient CDMA-based transmitter for high-speed serial links. Analog Integr Circ Sig Process 71, 343–348 (2012). https://doi.org/10.1007/s10470-012-9834-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-012-9834-7

Keywords

Navigation