Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

  • Juanjo Noguera
  • Stephen Neuendorffer
  • Sven Van Haastregt
  • Jesus Barba
  • Kees Vissers
  • Chris Dick
Article

DOI: 10.1007/s10470-011-9765-8

Cite this article as:
Noguera, J., Neuendorffer, S., Van Haastregt, S. et al. Analog Integr Circ Sig Process (2011) 69: 119. doi:10.1007/s10470-011-9765-8

Abstract

In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL’s AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.

Keywords

Sphere decoding High level synthesis FPGAs 

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Juanjo Noguera
    • 1
  • Stephen Neuendorffer
    • 2
  • Sven Van Haastregt
    • 3
  • Jesus Barba
    • 4
  • Kees Vissers
    • 2
  • Chris Dick
    • 2
  1. 1.Xilinx IrelandDublinIreland
  2. 2.Xilinx, IncSan JoseUSA
  3. 3.Leiden UniversityLeidenThe Netherlands
  4. 4.University of Castilla-La ManchaCiudad RealSpain

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