Analog Integrated Circuits and Signal Processing

, Volume 66, Issue 2, pp 223–233

A 1.0-mW, 71-dB SNDR, fourth-order ΣΔ interface circuit for MEMS microphones


  • Luca Picolli
    • Department of Electrical EngineeringUniversity of Pavia
  • Marco Grassi
    • Department of Electrical EngineeringUniversity of Pavia
  • Andrea Fornasari
    • National Semiconductor Corporation
    • Department of Electrical EngineeringUniversity of Pavia

DOI: 10.1007/s10470-010-9516-2

Cite this article as:
Picolli, L., Grassi, M., Fornasari, A. et al. Analog Integr Circ Sig Process (2011) 66: 223. doi:10.1007/s10470-010-9516-2


In this paper an integrated interface circuit for condenser MEMS microphones is presented. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order ΣΔ modulator and a fully-digital, single-bit, fourth-order ΣΔ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3 V, exhibits a current consumption of 215 μA for the analog part and 95 μA for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog ΣΔ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-μm CMOS process, occupies an area of 3 mm2, including pads.


MEMS microphoneΣΔ modulatorSensor interface circuitAudio integrated circuit

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© Springer Science+Business Media, LLC 2010