Analog Integrated Circuits and Signal Processing

, Volume 66, Issue 1, pp 49–59

A 5 GHz 90-nm CMOS all digital phase-locked loop

Authors

    • Electrical and Information TechnologyLund University
  • Henrik Sjöland
    • Electrical and Information TechnologyLund University
Article

DOI: 10.1007/s10470-010-9501-9

Cite this article as:
Lu, P. & Sjöland, H. Analog Integr Circ Sig Process (2011) 66: 49. doi:10.1007/s10470-010-9501-9

Abstract

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of −125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.

Keywords

All Digital Phase-Locked Loop (ADPLL)Time-to-Digital Converter (TDC)Phase Locked Loop (PLL)Digitally Controlled Oscillator (DCO)RFCMOS

Copyright information

© Springer Science+Business Media, LLC 2010