Analog Integrated Circuits and Signal Processing

, Volume 63, Issue 2, pp 321–327

Linear transconductor with flipped voltage follower in 130 nm CMOS

Authors

    • Electrical Communication Engineering DepartmentIndian Institute of Science Bangalore
  • Navakanta Bhat
    • Electrical Communication Engineering DepartmentIndian Institute of Science Bangalore
Article

DOI: 10.1007/s10470-009-9396-5

Cite this article as:
Ajayan, K.R. & Bhat, N. Analog Integr Circ Sig Process (2010) 63: 321. doi:10.1007/s10470-009-9396-5

Abstract

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

Keywords

CMOS analog circuitsThreshold voltage variabilityFlipped voltage followerAdaptive biasingLinear transconductor

1 Introduction

Transconductors are versatile building blocks for many applications in analog signal processing circuit area such as continuous—time filters, voltage controlled oscillators and current sensing circuits [1, 2]. Linearity is an important parameter for performance characterization of transconductors. Several reported transconductors were based on differential pairs, which achieve linearity using resistive source degeneration. It is a common approach to bias MOS transistors in the triode region as source degeneration devices.

The resulting topology is very compact in terms of silicon area, but linearity is often limited [3, 4]. Conventional differential pair (CDP) with a constant tail current was reported as a method of improving linearity [1, 5].

The linear input range of a conventional differential pair (CDP) with a constant tail current is heavily dependent on the quiescent value of the gate-to-source overdrive voltage [1]. In order to ensure the linearity of the operation of the transconductors, the MOS transistors must be biased to operate in strong inversion region, for that the gate-to-source overdrive voltage must be kept at least 100 mV. Beyond this limit, the devices tend to operate in moderate or weak inversion regions. In low-voltage CMOS circuits, this limits the linear input range of the CDP. Different approaches towards linearizing the transconductance of CDP have been presented in [59]. In ABDP circuit, an adaptive biasing scheme and source followers were used to generate a compensating tail current proportional to the differential input voltage. When ABDP circuit is mapped in to the 130 nm technology, the circuit fails to perform under technology scaling conditions.

An improved circuit is proposed in this paper by adaptively changing the biasing conditions of the tail current source transistors. Further to improve the current tailing performance the tail transistors are biased to operate in the triode region instead of saturation region in the ABDP circuit and the W/L ratio of the transistors is kept at the maximum. The source followers in ABDP are replaced with flipped voltage follower [10]. The Sect. 2 presents the limitations of ABDP circuit and Sect. 3 describes the proposed Linear Transconductor with Flipped Follower (LTFVF) circuit. The detailed performance comparison based on simulation results is presented in Sect. 4, followed by the process variability analysis in Sect. 5.

2 ABDP linear transconductor circuit

Adaptively biased differential pair (ABDP) linear transconductor circuit [1] is shown in Fig. 1. The transistors M1, M2, M3, and M4 are designed to operate in saturation. Neglecting the channel length modulation effects, the current through the MOSFET can be expressed as
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig1_HTML.gif
Fig. 1

ABDP circuit

$$ I_{D} = K\left( {{\frac{W}{L}}} \right)\left( {V_{GS} - V_{t} } \right)^{2} $$
(1)
$$ I_{D1} = K\left( {{\frac{W}{L}}} \right)_{1} \left( {V_{CM} + {\frac{{V_{id} }}{2}} - V_{S} - V_{t} } \right)^{2} $$
(2)
The matched transistor pair M1 and M2 have same (W/L) ratio so,
$$ I_{D2} = K\left( {{\frac{W}{L}}} \right)_{1} \left( {V_{CM} - {\frac{{V_{id} }}{2}} - V_{S} - V_{t} } \right)^{2} $$
(3)
where
$$ V_{GS1} = V_{1} - V_{S} = V_{CM} + {\frac{{V_{id} }}{2}} - V_{S} $$
(4)
$$ V_{GS2} = V_{2} - V_{S} = V_{CM} - {\frac{{V_{id} }}{2}} - V_{S} $$
(5)
$$ \Updelta I_{D} = I_{D1} - I_{D2} $$
(6)
$$ \Updelta I_{D} = K\left( {{\frac{W}{L}}} \right)_{1} V_{id} \left( {2{\text{V}}_{CM} - 2{\text{V}}_{S} - 2V_{t} } \right) $$
(7)
From the Eq. 7 the output differential current is a function of voltage at the source of the differential pair (VS). The voltage VS is not a constant in practical case and the value varies with input differential voltage. This is one of the main drawbacks of ABDP. A remedy for this is to keep VS as small as possible. But the minimum value of VS also depends on the input differential voltage (Vid), because M3, and M4 are designed to operate in saturation, the minimum voltage of VS to ensure M3 and M4 in saturation is \( V_{CM} + {\frac{{V_{id} }}{2}} - 2V_{t} , \) subsisting this value in Eq. 7
$$ \Updelta I_{D} = K\left( {{\frac{W}{L}}} \right)_{1} V_{id} \left( {2{\text{V}}_{\text{t}} - {\frac{{{\text{V}}_{\text{id}} }}{2}}} \right) $$
(8)
and
$$ Gm = {\frac{{\partial \Updelta I_{D} }}{{\partial {\text{V}}_{\text{id}} }}} \, = K\left( {{\frac{W}{L}}} \right)_{1} \left( {2{\text{V}}_{\text{t}} - {\text{V}}_{\text{id}} } \right) $$
(9)

From the above equations it is evident that linearity of transconductance suffers as Vid increases. So any variation in VS has a significant effect, and this will cause a nonlinearity of the transconductance, and this effect is very high when technology is scaled down.

The circuit is mapped on to the 130 nm technology, with same biasing conditions, but the circuit fails to perform under technology scaling conditions. An improvement in performance is observed, when the biasing condition of the tail current transistors is changed from saturation to triode region. This circuit is addressed as Improved Adaptively Biased Differential Pair (IABDP) linear transconductor circuit in the subsequent sections.

3 Linear transconductor with flipped voltage follower (LTFVF)

Linear transconductor circuit with flipped voltage follower is shown in Fig. 2. Transistors M5 and M7, M6 and M8 form two flipped voltage follower, which replace the adaptively biased source followers in the ABDP. M1 and M2 form the conventional differential pair with tail current transistors M3 and M4. Transistors M1 and M2 are biased in the saturation region and the tail current transistors M3, and M4 are in the triode region. The tail current transistors are biased in triode region so the voltage at the source of the differential pair (VS) can be made as low as possible and this is independent of the differential input voltage.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig2_HTML.gif
Fig. 2

LTFVF circuit

The transistors M1 and M2 are designed to operate in saturation. Neglecting the channel length modulation effects the differential output current ΔID can be found to have the same relation of Eq. 7. The transistors M3 and M4 are biased in the linear region of operation of the transistor, so the circuit can be designed with a very low value of voltage VS, and this reduces the dependence on VS. The current flowing through the transistor can be expressed as
$$ I_{D} = K\left( {{\frac{W}{L}}} \right)\left( {V_{GS} - V_{t} } \right)V_{DS} - {\frac{{V_{DS}^{2} }}{2}} $$
(10)
The matched transistor pair M3 and M4 have same (W/L) ratio so,
$$ I_{D3} = K\left( {{\frac{W}{L}}} \right)_{3} \left( {V_{CM} + {\frac{{V_{id} }}{2}} - 2V_{t} } \right)V_{S} - {\frac{{V_{S}^{2} }}{2}} $$
(11)
$$ I_{D4} = K\left( {{\frac{W}{L}}} \right)_{3} \left( {V_{CM} - {\frac{{V_{id} }}{2}} - 2V_{t} } \right)V_{S} - {\frac{{V_{S}^{2} }}{2}} $$
(12)
If the transistors are designed such a way that ID3 can be made equal to ID1 then all the current carried by M1 will be sunk in to M3. The value of VS can be found from Eq. 11 to 12
$$ {\text{V}}_{\text{S}} = {\frac{{\partial I_{\text{D}} }}{{K\left( {{\frac{W}{L}}} \right)_{3} V_{id} }}} $$
(13)
where
$$ \Updelta I_{D} = I_{D3} - I_{D4} $$
(14)
Applying Eqs. 13 in 7 and combine with Eqs. 6 and 14
$$ \Updelta I_{D} = K_{1} V_{id} \left( {2{\text{V}}_{\text{CM}} - 2\left( {{\frac{{\Updelta {\text{I}}_{\text{D}} }}{{K_{2} V_{id} }}}} \right) - 2V_{t} } \right) $$
(15)
$$ \Updelta I_{D} = {\frac{{2K_{1} V_{id} \left( {{\text{V}}_{\text{CM}} - {\text{V}}_{\text{t}} } \right)}}{{1 + \left( {{\raise0.7ex\hbox{${2K_{1} }$} \!\mathord{\left/ {\vphantom {{2K_{1} } {K_{2} }}}\right.\kern-\nulldelimiterspace} \!\lower0.7ex\hbox{${K_{2} }$}}} \right)}}} $$
(16)
where \( K_{1} = K\left( {{\frac{W}{L}}} \right)_{1} \) and \( K_{2} = K\left( {{\frac{W}{L}}} \right)_{ 3} . \) And if the transistors are designed such a way that \( K_{1} \ll K_{2} , \) then Eq. 16 can be approximated as
$$ \Updelta I_{D} = 2K_{1} V_{id} \left( {V_{CM} - V_{t} } \right) $$
(17)
$$ Gm = {\frac{{\partial \Updelta I_{D} }}{{\partial V_{id} }}} = 2K_{1} \left( {V_{CM} - V_{t} } \right) $$
(18)

So the proposed circuit will have a better linearity of transconductance over a wide range of Vid. Transistors pair M5 and M7, M6 and M8 form two flipped voltage followers, the gate of transistors M7 and M8 are connected to the drain of transistor M5 and M6, respectively, and this provides a negative shunt feedback. So any change in input voltage will try to change the drain voltage of M5 and this will try to change the current through M7, but M5 and M7 are driven by a constant current source, so the drain to source voltage of transistor M5 is adjusted to compensate the change in input voltage.

4 Simulation

The proposed LTFVF circuit shown in Fig. 2, was simulated in standard 130 nm technology CMOS process using umc13mmrf model files. The circuit was operated with Vdd of 1.2 V the performance of the LTFVF circuit is compared with ABDP and IABDP circuits. The dimensions of the various transistors and biasing conditions are summarized in Table 1.
Table 1

Simulation parameters

Parameter

ABDP

IABDP

LTFVF

Technology

130 nm

model

umc13mmrf

Vdd/Vt

1.2 V/230 mV

Vcm

900 mV

900 mV

900 mV

VS

200 mV

200 mV

15 mV

Vx

475 mV

475 mV

300 mV

I1(dc),I2(dc)

100 uA

100 uA

300 uA

Ibias

100 uA

100 uA

100 uA

(W/L)1,2

7.8u/2u

6.8u/2u

1.2u/240n

(W/L)4,3

40u/2u

100u/2u

100u/240n

(W/L)5.6

15u/2u

15u/2u

2u/240n

(W/L)7,8

60u/2u

60u/2u

2.5u/240n

(W/L)9

50u/2u

50u/2u

Not used

4.1 DC Transconductance

The DC transconductance of the circuits were analyzed by sweeping the differential input voltage from 600 to −600 mV and the results are plotted in Fig. 3. The proposed LTFVF circuit has a better linearity of DC transconductance for a 1 V(p–p) variation of the differential input voltage over the ABDP and IABDP circuits. When the differential input voltage is greater than 1 V, LTFVF and IABDP circuits have similar performance.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig3_HTML.gif
Fig. 3

Transconductance (DC) variation with differential input voltage

The percentage nonlinearity for the circuits is estimated and tabulated in Table 2. The proposed circuit has a better performance because the LTFVF circuit was biased with very low VS value, so the variations of VS will not reflect in the transconductance performance.
Table 2

DC Transconductance variation

Parameter

Variation of gm

Vid(p–p) (mV)

ABDP (%)

IABDP (%)

LTFVF (%)

250

2.47

0.31

0.15

500

6.36

1.24

0.78

1000

8.78

4.66

3.88

4.2 Output currents

The variation of output currents over a wide range of input differential voltages are examined and plotted in Fig. 4. From the results it is evident that the LTFVF and IABDP circuits exhibit better linearity of output current over a wide range of input voltage, but ABDP circuit fails to follow linear relation. After a differential input voltage range of 600 mV(p–p), the ABDP response changes to square-law relation. This saturation in output current is due to the large variation in VS of the ABDP circuit.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig4_HTML.gif
Fig. 4

Output current variation with differential input voltage

4.3 Biasing voltage variations

As explained in the Sect. 2, the design of VS in ABDP circuit is limited by the minimum value required to keep the transistors M3 and M4 in saturation. So any variation in input differential voltage has an effect in VS of the circuits, this limits the performance of the circuits. But in the case of LTFVF the transistors are in triode region, so the designer has the freedom to choose any small value of VS (Fig. 5).
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig5_HTML.gif
Fig. 5

VS variation with differential input voltage

Flipped voltage follower has a negative feedback mechanism, this ensures a variation of Vx with gain less than unity, and results an improvement in the tailing current efficiency of the tail current source. So this will ensure a condition ID1 equal to ID3 and results constant VS over a wide range of input. Thus the variation of VS is very small and has very less effect on output currents of LTFVF. This is the main advantage of LTFVF over the ABDP circuits. Figure 6 shows the variation of Vx with differential input voltage
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig6_HTML.gif
Fig. 6

Vx1 and Vx2 variation with differential input voltage

4.4 Dynamic transconductance

The dynamic transconductance of the circuits was analyzed in transient mode with an input signal frequency of 1, 10, and 100 MHz and amplitude variation of −500 to 500 mV differential AC input signal.

Figure 7 shows the transconductance response at 100 MHz. The variation of gain is tabulated in Table 3. The proposed circuit has a better linearity (>1.5%) over both circuits in 1 V (p–p) input condition.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig7_HTML.gif
Fig. 7

Transconductance (AC) variation with differential input voltage

Table 3

Dynamic transconductance variation

Vac(p–p)

ABDP

IABDP

LTFVF

Gm variation in % (1 MHz)

 500 mV

2.27

0.06

0.01

 1 V

4.78

1.7

0.09

Gm variation in % (10 MHz)

 500 mV

2.27

0.06

0.01

 1 V

4.78

2

0.09

Gm variation in %(100 MHz)

 500 mV

1.57

0.06

0.02

 1 V

2.537

2

0.09

4.5 Transconductance variation with common mode signal

The variation of transconductance of the circuits was analyzed in transient mode with input signal amplitude of 100 mV at 100 MHz and for a common mode signal variation from 600 to 1,200 mV. The response is plotted in Fig. 8. LTFVF circuit exhibits a constant transconductance from a common mode input voltage of 850 mV to 1.2 V. IABDP circuit offers better transconductance from 700 mV, but the transconductance varies in the full span of common mode signal.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig8_HTML.gif
Fig. 8

Transconductance (AC) variation with common mode input voltage

The performance of the circuits was analyzed for common mode voltage variation with different input differential voltages (10, 50, and 100 mV), the performance was exactly the same for all input conditions. The percentage of variation in gm with common mode voltage for an input differential voltage of 100 mV is tabulated in Table 4. The transconductance at common mode voltage of 900 mV is taken as reference for calculating percentage.
Table 4

Common mode transconductance variation

Vcm

ABDP (%)

IABDP (%)

LTFVF (%)

800 mV

40

10

12

850 mV

20

5

2.5

1 V

14

7.1

2

1.2 V

31

16.2

4.3

4.6 Common mode drain current variation with frequency

The common mode drain current variation of ABDP, IABDP and LTFVF were plotted in Fig. 9. The proposed LTFVF circuit offers constant performance over a wide range of high frequency region and for other two circuit common mode current starts to change at frequencies above 10 MHz. The performance of the proposed circuit is 1 dB better than IABDP and 6 dB better than ABDP circuit.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig9_HTML.gif
Fig. 9

Common mode current variation with input frequency

4.7 Differential mode output current variation with frequency

The differential mode output current variation with frequency for ABDP, IABDP and LTFVF circuits are plotted in Fig. 10. The proposed LTFVF circuits has constant performance over a wide range of frequency region, and for other two circuits common mode current starts to change at frequencies above 10 MHz. The common mode rejection ratio (CMRR) of the circuits are determined from the simulation, CMMR of LTFVF, IABDP and ABDP are 6,300, 6,300, and 500 dB, respectively, at 10 MHz. Only LTFVF circuit has constant CMRR over a wide frequency range.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig10_HTML.gif
Fig. 10

Differential mode output current variation with input frequency

4.8 Total harmonic distortion analysis

The noise performance of the ABDP, IABDP and LTFVF circuits was simulated with 1 V p–p sinusoidal signal over a range of frequencies from 1 to 100 MHz, and THD is plotted in Fig. 11. The proposed LTFVF circuit has 6 dB improvement in THD over IABDP circuit and 16 dB over ABDP circuit.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig11_HTML.gif
Fig. 11

THD variation with frequency

5 Variability analysis

In this section the circuit performance under processes variability is analyzed by modeling processes variability in terms of threshold voltage variation.

The matched transistors M1 and M2 are introduced to have ±5% or ±10% Vt variation from the nominal value of 230 mV. The DC analysis was conducted with mismatched transistor pair in differential configuration and net mismatch introduced was 10 and 20%, Fig. 12 shows the variation of transconductance.
https://static-content.springer.com/image/art%3A10.1007%2Fs10470-009-9396-5/MediaObjects/10470_2009_9396_Fig12_HTML.gif
Fig. 12

Transconductance variation with differential input voltage under mismatch

The percentage variation of transconductance with the value of transconductance without mismatch is tabulated in Table 5. LTFVF circuit is very robust against processes variation.
Table 5

Transconductance variation under variability condition

∂Vt (%)

ABDP (%)

IABDP (%)

LTFVF (%)

5

7.5

0.03

0.009

10

16.1

0.07

0.02

6 Conclusion

A modified design of adaptively biased differential transconductor (IABDP) circuit is suggested. To further improve the transconductance linearity a new circuit is proposed. The design of Linear Transconductor with Flipped Voltage Follower (LTFVF) is described. The circuit was simulated 130 nm technology using um13mmrf model files.

The proposed LTFVF circuit outperforms the ABDP circuit due to better current tailing of the input transistors enabled with a negative shunt feedback of flipped voltage follower. LTFVF has better linearity over a wide range of common mode and differential mode input range. The harmonic distortion is 16 dB better for LTFVF and the circuit is also robust against process induced threshold voltage variability.

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