# Linear transconductor with flipped voltage follower in 130 nm CMOS

## Authors

- First Online:

- Received:
- Revised:
- Accepted:

DOI: 10.1007/s10470-009-9396-5

- Cite this article as:
- Ajayan, K.R. & Bhat, N. Analog Integr Circ Sig Process (2010) 63: 321. doi:10.1007/s10470-009-9396-5

- 4 Citations
- 205 Views

## Abstract

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

### Keywords

CMOS analog circuitsThreshold voltage variabilityFlipped voltage followerAdaptive biasingLinear transconductor## 1 Introduction

Transconductors are versatile building blocks for many applications in analog signal processing circuit area such as continuous—time filters, voltage controlled oscillators and current sensing circuits [1, 2]. Linearity is an important parameter for performance characterization of transconductors. Several reported transconductors were based on differential pairs, which achieve linearity using resistive source degeneration. It is a common approach to bias MOS transistors in the triode region as source degeneration devices.

The resulting topology is very compact in terms of silicon area, but linearity is often limited [3, 4]. Conventional differential pair (CDP) with a constant tail current was reported as a method of improving linearity [1, 5].

The linear input range of a conventional differential pair (CDP) with a constant tail current is heavily dependent on the quiescent value of the gate-to-source overdrive voltage [1]. In order to ensure the linearity of the operation of the transconductors, the MOS transistors must be biased to operate in strong inversion region, for that the gate-to-source overdrive voltage must be kept at least 100 mV. Beyond this limit, the devices tend to operate in moderate or weak inversion regions. In low-voltage CMOS circuits, this limits the linear input range of the CDP. Different approaches towards linearizing the transconductance of CDP have been presented in [5–9]. In ABDP circuit, an adaptive biasing scheme and source followers were used to generate a compensating tail current proportional to the differential input voltage. When ABDP circuit is mapped in to the 130 nm technology, the circuit fails to perform under technology scaling conditions.

An improved circuit is proposed in this paper by adaptively changing the biasing conditions of the tail current source transistors. Further to improve the current tailing performance the tail transistors are biased to operate in the triode region instead of saturation region in the ABDP circuit and the W/L ratio of the transistors is kept at the maximum. The source followers in ABDP are replaced with flipped voltage follower [10]. The Sect. 2 presents the limitations of ABDP circuit and Sect. 3 describes the proposed Linear Transconductor with Flipped Follower (LTFVF) circuit. The detailed performance comparison based on simulation results is presented in Sect. 4, followed by the process variability analysis in Sect. 5.

## 2 ABDP linear transconductor circuit

_{S}). The voltage V

_{S}is not a constant in practical case and the value varies with input differential voltage. This is one of the main drawbacks of ABDP. A remedy for this is to keep V

_{S}as small as possible. But the minimum value of V

_{S}also depends on the input differential voltage (V

_{id}), because M3, and M4 are designed to operate in saturation, the minimum voltage of V

_{S}to ensure M3 and M4 in saturation is \( V_{CM} + {\frac{{V_{id} }}{2}} - 2V_{t} , \) subsisting this value in Eq. 7

From the above equations it is evident that linearity of transconductance suffers as V_{id} increases. So any variation in V_{S} has a significant effect, and this will cause a nonlinearity of the transconductance, and this effect is very high when technology is scaled down.

The circuit is mapped on to the 130 nm technology, with same biasing conditions, but the circuit fails to perform under technology scaling conditions. An improvement in performance is observed, when the biasing condition of the tail current transistors is changed from saturation to triode region. This circuit is addressed as Improved Adaptively Biased Differential Pair (IABDP) linear transconductor circuit in the subsequent sections.

## 3 Linear transconductor with flipped voltage follower (LTFVF)

_{S}) can be made as low as possible and this is independent of the differential input voltage.

*I*

_{D}can be found to have the same relation of Eq. 7. The transistors M3 and M4 are biased in the linear region of operation of the transistor, so the circuit can be designed with a very low value of voltage V

_{S}, and this reduces the dependence on V

_{S}. The current flowing through the transistor can be expressed as

_{D3}can be made equal to I

_{D1}then all the current carried by M1 will be sunk in to M3. The value of V

_{S}can be found from Eq. 11 to 12

So the proposed circuit will have a better linearity of transconductance over a wide range of V_{id}. Transistors pair M5 and M7, M6 and M8 form two flipped voltage followers, the gate of transistors M7 and M8 are connected to the drain of transistor M5 and M6, respectively, and this provides a negative shunt feedback. So any change in input voltage will try to change the drain voltage of M5 and this will try to change the current through M7, but M5 and M7 are driven by a constant current source, so the drain to source voltage of transistor M5 is adjusted to compensate the change in input voltage.

## 4 Simulation

_{dd}of 1.2 V the performance of the LTFVF circuit is compared with ABDP and IABDP circuits. The dimensions of the various transistors and biasing conditions are summarized in Table 1.

Simulation parameters

Parameter | ABDP | IABDP | LTFVF |
---|---|---|---|

Technology | 130 nm | ||

model | umc13mmrf | ||

V | 1.2 V/230 mV | ||

V | 900 mV | 900 mV | 900 mV |

V | 200 mV | 200 mV | 15 mV |

V | 475 mV | 475 mV | 300 mV |

I1(dc),I2(dc) | 100 uA | 100 uA | 300 uA |

Ibias | 100 uA | 100 uA | 100 uA |

(W/L)1,2 | 7.8u/2u | 6.8u/2u | 1.2u/240n |

(W/L)4,3 | 40u/2u | 100u/2u | 100u/240n |

(W/L)5.6 | 15u/2u | 15u/2u | 2u/240n |

(W/L)7,8 | 60u/2u | 60u/2u | 2.5u/240n |

(W/L)9 | 50u/2u | 50u/2u | Not used |

### 4.1 DC Transconductance

_{S}value, so the variations of V

_{S}will not reflect in the transconductance performance.

DC Transconductance variation

Parameter | Variation of gm | ||
---|---|---|---|

V | ABDP (%) | IABDP (%) | LTFVF (%) |

250 | 2.47 | 0.31 | 0.15 |

500 | 6.36 | 1.24 | 0.78 |

1000 | 8.78 | 4.66 | 3.88 |

### 4.2 Output currents

_{S}of the ABDP circuit.

### 4.3 Biasing voltage variations

_{S}in ABDP circuit is limited by the minimum value required to keep the transistors M3 and M4 in saturation. So any variation in input differential voltage has an effect in V

_{S}of the circuits, this limits the performance of the circuits. But in the case of LTFVF the transistors are in triode region, so the designer has the freedom to choose any small value of V

_{S}(Fig. 5).

_{x}with gain less than unity, and results an improvement in the tailing current efficiency of the tail current source. So this will ensure a condition I

_{D1}equal to I

_{D3}and results constant V

_{S}over a wide range of input. Thus the variation of V

_{S}is very small and has very less effect on output currents of LTFVF. This is the main advantage of LTFVF over the ABDP circuits. Figure 6 shows the variation of V

_{x}with differential input voltage

### 4.4 Dynamic transconductance

The dynamic transconductance of the circuits was analyzed in transient mode with an input signal frequency of 1, 10, and 100 MHz and amplitude variation of −500 to 500 mV differential AC input signal.

Dynamic transconductance variation

V | ABDP | IABDP | LTFVF |
---|---|---|---|

Gm variation in % (1 MHz) | |||

500 mV | 2.27 | 0.06 | 0.01 |

1 V | 4.78 | 1.7 | 0.09 |

Gm variation in % (10 MHz) | |||

500 mV | 2.27 | 0.06 | 0.01 |

1 V | 4.78 | 2 | 0.09 |

Gm variation in %(100 MHz) | |||

500 mV | 1.57 | 0.06 | 0.02 |

1 V | 2.537 | 2 | 0.09 |

### 4.5 Transconductance variation with common mode signal

_{m}with common mode voltage for an input differential voltage of 100 mV is tabulated in Table 4. The transconductance at common mode voltage of 900 mV is taken as reference for calculating percentage.

Common mode transconductance variation

V | ABDP (%) | IABDP (%) | LTFVF (%) |
---|---|---|---|

800 mV | 40 | 10 | 12 |

850 mV | 20 | 5 | 2.5 |

1 V | 14 | 7.1 | 2 |

1.2 V | 31 | 16.2 | 4.3 |

### 4.6 Common mode drain current variation with frequency

### 4.7 Differential mode output current variation with frequency

### 4.8 Total harmonic distortion analysis

## 5 Variability analysis

In this section the circuit performance under processes variability is analyzed by modeling processes variability in terms of threshold voltage variation.

_{t}variation from the nominal value of 230 mV. The DC analysis was conducted with mismatched transistor pair in differential configuration and net mismatch introduced was 10 and 20%, Fig. 12 shows the variation of transconductance.

Transconductance variation under variability condition

∂V | ABDP (%) | IABDP (%) | LTFVF (%) |
---|---|---|---|

5 | 7.5 | 0.03 | 0.009 |

10 | 16.1 | 0.07 | 0.02 |

## 6 Conclusion

A modified design of adaptively biased differential transconductor (IABDP) circuit is suggested. To further improve the transconductance linearity a new circuit is proposed. The design of Linear Transconductor with Flipped Voltage Follower (LTFVF) is described. The circuit was simulated 130 nm technology using um13mmrf model files.

The proposed LTFVF circuit outperforms the ABDP circuit due to better current tailing of the input transistors enabled with a negative shunt feedback of flipped voltage follower. LTFVF has better linearity over a wide range of common mode and differential mode input range. The harmonic distortion is 16 dB better for LTFVF and the circuit is also robust against process induced threshold voltage variability.